103 lines
2 KiB
C
103 lines
2 KiB
C
#ifndef __ARM_REGFORMAT_H__
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#define __ARM_REGFORMAT_H__
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enum arm_regno{
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R0 = 0,
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R1,
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R2,
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R3,
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R4,
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R5,
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R6,
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R7,
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R8,
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R9,
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R10,
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R11,
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R12,
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R13,
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LR,
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R15, //PC,
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CPSR_REG,
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SPSR_REG,
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#if 1
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PHYS_PC,
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R13_USR,
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R14_USR,
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R13_SVC,
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R14_SVC,
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R13_ABORT,
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R14_ABORT,
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R13_UNDEF,
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R14_UNDEF,
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R13_IRQ,
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R14_IRQ,
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R8_FIRQ,
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R9_FIRQ,
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R10_FIRQ,
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R11_FIRQ,
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R12_FIRQ,
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R13_FIRQ,
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R14_FIRQ,
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SPSR_INVALID1,
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SPSR_INVALID2,
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SPSR_SVC,
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SPSR_ABORT,
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SPSR_UNDEF,
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SPSR_IRQ,
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SPSR_FIRQ,
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MODE_REG, /* That is the cpsr[4 : 0], just for calculation easily */
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BANK_REG,
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EXCLUSIVE_TAG,
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EXCLUSIVE_STATE,
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EXCLUSIVE_RESULT,
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CP15_BASE,
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CP15_C0 = CP15_BASE,
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CP15_C0_C0 = CP15_C0,
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CP15_MAIN_ID = CP15_C0_C0,
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CP15_CACHE_TYPE,
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CP15_TCM_STATUS,
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CP15_TLB_TYPE,
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CP15_C0_C1,
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CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
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CP15_PROCESSOR_FEATURE_1,
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CP15_DEBUG_FEATURE_0,
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CP15_AUXILIARY_FEATURE_0,
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CP15_C1_C0,
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CP15_CONTROL = CP15_C1_C0,
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CP15_AUXILIARY_CONTROL,
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CP15_COPROCESSOR_ACCESS_CONTROL,
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CP15_C2,
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CP15_C2_C0 = CP15_C2,
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CP15_TRANSLATION_BASE = CP15_C2_C0,
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CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE,
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CP15_TRANSLATION_BASE_TABLE_1,
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CP15_TRANSLATION_BASE_CONTROL,
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CP15_DOMAIN_ACCESS_CONTROL,
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CP15_RESERVED,
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/* Fault status */
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CP15_FAULT_STATUS,
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CP15_INSTR_FAULT_STATUS,
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CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
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CP15_INST_FSR,
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/* Fault Address register */
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CP15_FAULT_ADDRESS,
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CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
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CP15_WFAR,
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CP15_IFAR,
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CP15_PID,
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CP15_CONTEXT_ID,
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CP15_THREAD_URO,
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CP15_TLB_FAULT_ADDR, /* defined by SkyEye */
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CP15_TLB_FAULT_STATUS, /* defined by SkyEye */
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/* VFP registers */
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VFP_BASE,
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VFP_FPSID = VFP_BASE,
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VFP_FPSCR,
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VFP_FPEXC,
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#endif
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MAX_REG_NUM,
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};
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#define VFP_OFFSET(x) (x - VFP_BASE)
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#endif
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