246 lines
11 KiB
C++
246 lines
11 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "command_processor.h"
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#include "math.h"
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#include "pica.h"
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#include "primitive_assembly.h"
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#include "vertex_shader.h"
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#include "debug_utils/debug_utils.h"
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namespace Pica {
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Regs registers;
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namespace CommandProcessor {
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static int float_regs_counter = 0;
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static u32 uniform_write_buffer[4];
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// Used for VSLoadProgramData and VSLoadSwizzleData
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static u32 vs_binary_write_offset = 0;
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static u32 vs_swizzle_write_offset = 0;
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static inline void WritePicaReg(u32 id, u32 value) {
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u32 old_value = registers[id];
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registers[id] = value;
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switch(id) {
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// It seems like these trigger vertex rendering
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case PICA_REG_INDEX(trigger_draw):
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case PICA_REG_INDEX(trigger_draw_indexed):
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{
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const auto& attribute_config = registers.vertex_attributes;
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const u8* const base_address = Memory::GetPointer(attribute_config.GetBaseAddress());
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// Information about internal vertex attributes
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const u8* vertex_attribute_sources[16];
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u32 vertex_attribute_strides[16];
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u32 vertex_attribute_formats[16];
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u32 vertex_attribute_elements[16];
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u32 vertex_attribute_element_size[16];
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// Setup attribute data from loaders
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for (int loader = 0; loader < 12; ++loader) {
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const auto& loader_config = attribute_config.attribute_loaders[loader];
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const u8* load_address = base_address + loader_config.data_offset;
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// TODO: What happens if a loader overwrites a previous one's data?
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for (int component = 0; component < loader_config.component_count; ++component) {
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u32 attribute_index = loader_config.GetComponent(component);
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vertex_attribute_sources[attribute_index] = load_address;
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vertex_attribute_strides[attribute_index] = loader_config.byte_count;
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vertex_attribute_formats[attribute_index] = (u32)attribute_config.GetFormat(attribute_index);
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vertex_attribute_elements[attribute_index] = attribute_config.GetNumElements(attribute_index);
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vertex_attribute_element_size[attribute_index] = attribute_config.GetElementSizeInBytes(attribute_index);
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load_address += attribute_config.GetStride(attribute_index);
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}
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}
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// Load vertices
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bool is_indexed = (id == PICA_REG_INDEX(trigger_draw_indexed));
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const auto& index_info = registers.index_array;
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const u8* index_address_8 = (u8*)base_address + index_info.offset;
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const u16* index_address_16 = (u16*)index_address_8;
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bool index_u16 = (bool)index_info.format;
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DebugUtils::GeometryDumper geometry_dumper;
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for (int index = 0; index < registers.num_vertices; ++index)
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{
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int vertex = is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index]) : index;
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if (is_indexed) {
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// TODO: Implement some sort of vertex cache!
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}
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// Initialize data for the current vertex
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VertexShader::InputVertex input;
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for (int i = 0; i < attribute_config.GetNumTotalAttributes(); ++i) {
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for (int comp = 0; comp < vertex_attribute_elements[i]; ++comp) {
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const u8* srcdata = vertex_attribute_sources[i] + vertex_attribute_strides[i] * vertex + comp * vertex_attribute_element_size[i];
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const float srcval = (vertex_attribute_formats[i] == 0) ? *(s8*)srcdata :
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(vertex_attribute_formats[i] == 1) ? *(u8*)srcdata :
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(vertex_attribute_formats[i] == 2) ? *(s16*)srcdata :
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*(float*)srcdata;
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input.attr[i][comp] = float24::FromFloat32(srcval);
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DEBUG_LOG(GPU, "Loaded component %x of attribute %x for vertex %x (index %x) from 0x%08x + 0x%08x + 0x%04x: %f",
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comp, i, vertex, index,
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attribute_config.GetBaseAddress(),
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vertex_attribute_sources[i] - base_address,
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srcdata - vertex_attribute_sources[i],
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input.attr[i][comp].ToFloat32());
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}
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}
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// NOTE: For now, we simply assume that the first input attribute corresponds to the position.
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geometry_dumper.AddVertex({input.attr[0][0].ToFloat32(), input.attr[0][1].ToFloat32(), input.attr[0][2].ToFloat32()}, registers.triangle_topology);
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VertexShader::OutputVertex output = VertexShader::RunShader(input, attribute_config.GetNumTotalAttributes());
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if (is_indexed) {
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// TODO: Add processed vertex to vertex cache!
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}
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PrimitiveAssembly::SubmitVertex(output);
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}
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geometry_dumper.Dump();
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break;
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}
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[0], 0x2c1):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[1], 0x2c2):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[2], 0x2c3):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[3], 0x2c4):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[4], 0x2c5):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[5], 0x2c6):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[6], 0x2c7):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[7], 0x2c8):
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{
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auto& uniform_setup = registers.vs_uniform_setup;
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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uniform_write_buffer[float_regs_counter++] = value;
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// Uniforms are written in a packed format such that 4 float24 values are encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) ||
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(float_regs_counter >= 3 && !uniform_setup.IsFloat32())) {
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float_regs_counter = 0;
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auto& uniform = VertexShader::GetFloatUniform(uniform_setup.index);
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if (uniform_setup.index > 95) {
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ERROR_LOG(GPU, "Invalid VS uniform index %d", (int)uniform_setup.index);
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break;
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}
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// NOTE: The destination component order indeed is "backwards"
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if (uniform_setup.IsFloat32()) {
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for (auto i : {0,1,2,3})
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uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i]));
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} else {
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// TODO: Untested
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uniform.w = float24::FromRawFloat24(uniform_write_buffer[0] >> 8);
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uniform.z = float24::FromRawFloat24(((uniform_write_buffer[0] & 0xFF)<<16) | ((uniform_write_buffer[1] >> 16) & 0xFFFF));
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uniform.y = float24::FromRawFloat24(((uniform_write_buffer[1] & 0xFFFF)<<8) | ((uniform_write_buffer[2] >> 24) & 0xFF));
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uniform.x = float24::FromRawFloat24(uniform_write_buffer[2] & 0xFFFFFF);
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}
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DEBUG_LOG(GPU, "Set uniform %x to (%f %f %f %f)", (int)uniform_setup.index,
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uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(),
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uniform.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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uniform_setup.index = uniform_setup.index + 1;
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}
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break;
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}
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// Seems to be used to reset the write pointer for VSLoadProgramData
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case PICA_REG_INDEX(vs_program.begin_load):
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vs_binary_write_offset = 0;
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break;
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// Load shader program code
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[2], 0x2ce):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[3], 0x2cf):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[4], 0x2d0):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[5], 0x2d1):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[6], 0x2d2):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[7], 0x2d3):
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{
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VertexShader::SubmitShaderMemoryChange(vs_binary_write_offset, value);
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vs_binary_write_offset++;
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break;
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}
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// Seems to be used to reset the write pointer for VSLoadSwizzleData
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case PICA_REG_INDEX(vs_swizzle_patterns.begin_load):
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vs_swizzle_write_offset = 0;
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break;
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// Load swizzle pattern data
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[0], 0x2d6):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[1], 0x2d7):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[2], 0x2d8):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[3], 0x2d9):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[4], 0x2da):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[5], 0x2db):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[6], 0x2dc):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[7], 0x2dd):
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{
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VertexShader::SubmitSwizzleDataChange(vs_swizzle_write_offset, value);
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vs_swizzle_write_offset++;
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break;
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}
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default:
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break;
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}
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}
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static std::ptrdiff_t ExecuteCommandBlock(const u32* first_command_word) {
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const CommandHeader& header = *(const CommandHeader*)(&first_command_word[1]);
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u32* read_pointer = (u32*)first_command_word;
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// TODO: Take parameter mask into consideration!
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WritePicaReg(header.cmd_id, *read_pointer);
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read_pointer += 2;
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for (int i = 1; i < 1+header.extra_data_length; ++i) {
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u32 cmd = header.cmd_id + ((header.group_commands) ? i : 0);
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WritePicaReg(cmd, *read_pointer);
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++read_pointer;
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}
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// align read pointer to 8 bytes
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if ((first_command_word - read_pointer) % 2)
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++read_pointer;
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return read_pointer - first_command_word;
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}
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void ProcessCommandList(const u32* list, u32 size) {
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u32* read_pointer = (u32*)list;
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while (read_pointer < list + size) {
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read_pointer += ExecuteCommandBlock(read_pointer);
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}
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}
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} // namespace
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} // namespace
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