611 lines
22 KiB
C++
611 lines
22 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cstring>
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#include <numeric>
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#include <type_traits>
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#include "common/color.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/math_util.h"
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#include "common/microprofile.h"
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#include "common/thread.h"
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#include "common/timer.h"
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#include "common/vector_math.h"
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#include "core/core_timing.h"
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#include "core/hle/service/gsp_gpu.h"
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#include "core/hle/service/hid/hid.h"
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#include "core/hw/gpu.h"
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#include "core/hw/hw.h"
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#include "core/memory.h"
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#include "core/settings.h"
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#include "core/tracer/recorder.h"
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#include "video_core/command_processor.h"
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#include "video_core/debug_utils/debug_utils.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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#include "video_core/utils.h"
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#include "video_core/video_core.h"
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namespace GPU {
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Regs g_regs;
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/// 268MHz CPU clocks / 60Hz frames per second
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const u64 frame_ticks = 268123480ull / 60;
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/// Event id for CoreTiming
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static int vblank_event;
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/// Total number of frames drawn
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static u64 frame_count;
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/// Start clock for frame limiter
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static u32 time_point;
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/// Total delay caused by slow frames
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static float time_delay;
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constexpr float FIXED_FRAME_TIME = 1000.0f / 60;
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// Max lag caused by slow frames. Can be adjusted to compensate for too many slow frames. Higher
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// values increases time needed to limit frame rate after spikes
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constexpr float MAX_LAG_TIME = 18;
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template <typename T>
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inline void Read(T& var, const u32 raw_addr) {
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u32 addr = raw_addr - HW::VADDR_GPU;
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u32 index = addr / 4;
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// Reads other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
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LOG_ERROR(HW_GPU, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, addr);
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return;
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}
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var = g_regs[addr / 4];
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}
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static Math::Vec4<u8> DecodePixel(Regs::PixelFormat input_format, const u8* src_pixel) {
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switch (input_format) {
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case Regs::PixelFormat::RGBA8:
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return Color::DecodeRGBA8(src_pixel);
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case Regs::PixelFormat::RGB8:
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return Color::DecodeRGB8(src_pixel);
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case Regs::PixelFormat::RGB565:
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return Color::DecodeRGB565(src_pixel);
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case Regs::PixelFormat::RGB5A1:
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return Color::DecodeRGB5A1(src_pixel);
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case Regs::PixelFormat::RGBA4:
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return Color::DecodeRGBA4(src_pixel);
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default:
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LOG_ERROR(HW_GPU, "Unknown source framebuffer format %x", input_format);
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return {0, 0, 0, 0};
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}
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}
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MICROPROFILE_DEFINE(GPU_DisplayTransfer, "GPU", "DisplayTransfer", MP_RGB(100, 100, 255));
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MICROPROFILE_DEFINE(GPU_CmdlistProcessing, "GPU", "Cmdlist Processing", MP_RGB(100, 255, 100));
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static void MemoryFill(const Regs::MemoryFillConfig& config) {
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const PAddr start_addr = config.GetStartAddress();
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const PAddr end_addr = config.GetEndAddress();
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// TODO: do hwtest with these cases
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if (!Memory::IsValidPhysicalAddress(start_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid start address 0x%08X", start_addr);
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return;
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}
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if (!Memory::IsValidPhysicalAddress(end_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid end address 0x%08X", end_addr);
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return;
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}
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if (end_addr <= start_addr) {
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LOG_CRITICAL(HW_GPU, "invalid memory range from 0x%08X to 0x%08X", start_addr, end_addr);
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return;
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}
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u8* start = Memory::GetPhysicalPointer(start_addr);
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u8* end = Memory::GetPhysicalPointer(end_addr);
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// TODO: Consider always accelerating and returning vector of
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// regions that the accelerated fill did not cover to
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// reduce/eliminate the fill that the cpu has to do.
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// This would also mean that the flush below is not needed.
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// Fill should first flush all surfaces that touch but are
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// not completely within the fill range.
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// Then fill all completely covered surfaces, and return the
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// regions that were between surfaces or within the touching
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// ones for cpu to manually fill here.
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if (VideoCore::g_renderer->Rasterizer()->AccelerateFill(config))
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return;
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Memory::RasterizerFlushAndInvalidateRegion(config.GetStartAddress(),
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config.GetEndAddress() - config.GetStartAddress());
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if (config.fill_24bit) {
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// fill with 24-bit values
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for (u8* ptr = start; ptr < end; ptr += 3) {
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ptr[0] = config.value_24bit_r;
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ptr[1] = config.value_24bit_g;
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ptr[2] = config.value_24bit_b;
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}
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} else if (config.fill_32bit) {
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// fill with 32-bit values
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if (end > start) {
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u32 value = config.value_32bit;
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size_t len = (end - start) / sizeof(u32);
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for (size_t i = 0; i < len; ++i)
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memcpy(&start[i * sizeof(u32)], &value, sizeof(u32));
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}
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} else {
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// fill with 16-bit values
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u16 value_16bit = config.value_16bit.Value();
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for (u8* ptr = start; ptr < end; ptr += sizeof(u16))
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memcpy(ptr, &value_16bit, sizeof(u16));
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}
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}
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static void DisplayTransfer(const Regs::DisplayTransferConfig& config) {
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const PAddr src_addr = config.GetPhysicalInputAddress();
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const PAddr dst_addr = config.GetPhysicalOutputAddress();
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// TODO: do hwtest with these cases
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if (!Memory::IsValidPhysicalAddress(src_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid input address 0x%08X", src_addr);
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return;
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}
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if (!Memory::IsValidPhysicalAddress(dst_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid output address 0x%08X", dst_addr);
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return;
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}
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if (config.input_width == 0) {
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LOG_CRITICAL(HW_GPU, "zero input width");
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return;
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}
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if (config.input_height == 0) {
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LOG_CRITICAL(HW_GPU, "zero input height");
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return;
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}
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if (config.output_width == 0) {
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LOG_CRITICAL(HW_GPU, "zero output width");
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return;
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}
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if (config.output_height == 0) {
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LOG_CRITICAL(HW_GPU, "zero output height");
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return;
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}
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if (VideoCore::g_renderer->Rasterizer()->AccelerateDisplayTransfer(config))
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return;
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u8* src_pointer = Memory::GetPhysicalPointer(src_addr);
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u8* dst_pointer = Memory::GetPhysicalPointer(dst_addr);
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if (config.scaling > config.ScaleXY) {
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LOG_CRITICAL(HW_GPU, "Unimplemented display transfer scaling mode %u",
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config.scaling.Value());
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UNIMPLEMENTED();
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return;
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}
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if (config.input_linear && config.scaling != config.NoScale) {
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LOG_CRITICAL(HW_GPU, "Scaling is only implemented on tiled input");
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UNIMPLEMENTED();
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return;
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}
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int horizontal_scale = config.scaling != config.NoScale ? 1 : 0;
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int vertical_scale = config.scaling == config.ScaleXY ? 1 : 0;
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u32 output_width = config.output_width >> horizontal_scale;
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u32 output_height = config.output_height >> vertical_scale;
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u32 input_size =
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config.input_width * config.input_height * GPU::Regs::BytesPerPixel(config.input_format);
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u32 output_size = output_width * output_height * GPU::Regs::BytesPerPixel(config.output_format);
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Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(), input_size);
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Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(), output_size);
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for (u32 y = 0; y < output_height; ++y) {
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for (u32 x = 0; x < output_width; ++x) {
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Math::Vec4<u8> src_color;
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// Calculate the [x,y] position of the input image
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// based on the current output position and the scale
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u32 input_x = x << horizontal_scale;
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u32 input_y = y << vertical_scale;
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u32 output_y;
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if (config.flip_vertically) {
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// Flip the y value of the output data,
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// we do this after calculating the [x,y] position of the input image
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// to account for the scaling options.
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output_y = output_height - y - 1;
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} else {
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output_y = y;
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}
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u32 dst_bytes_per_pixel = GPU::Regs::BytesPerPixel(config.output_format);
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u32 src_bytes_per_pixel = GPU::Regs::BytesPerPixel(config.input_format);
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u32 src_offset;
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u32 dst_offset;
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if (config.input_linear) {
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if (!config.dont_swizzle) {
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// Interpret the input as linear and the output as tiled
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u32 coarse_y = output_y & ~7;
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u32 stride = output_width * dst_bytes_per_pixel;
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src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel;
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dst_offset = VideoCore::GetMortonOffset(x, output_y, dst_bytes_per_pixel) +
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coarse_y * stride;
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} else {
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// Both input and output are linear
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src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel;
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dst_offset = (x + output_y * output_width) * dst_bytes_per_pixel;
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}
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} else {
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if (!config.dont_swizzle) {
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// Interpret the input as tiled and the output as linear
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u32 coarse_y = input_y & ~7;
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u32 stride = config.input_width * src_bytes_per_pixel;
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src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) +
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coarse_y * stride;
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dst_offset = (x + output_y * output_width) * dst_bytes_per_pixel;
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} else {
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// Both input and output are tiled
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u32 out_coarse_y = output_y & ~7;
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u32 out_stride = output_width * dst_bytes_per_pixel;
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u32 in_coarse_y = input_y & ~7;
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u32 in_stride = config.input_width * src_bytes_per_pixel;
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src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) +
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in_coarse_y * in_stride;
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dst_offset = VideoCore::GetMortonOffset(x, output_y, dst_bytes_per_pixel) +
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out_coarse_y * out_stride;
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}
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}
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const u8* src_pixel = src_pointer + src_offset;
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src_color = DecodePixel(config.input_format, src_pixel);
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if (config.scaling == config.ScaleX) {
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Math::Vec4<u8> pixel =
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DecodePixel(config.input_format, src_pixel + src_bytes_per_pixel);
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src_color = ((src_color + pixel) / 2).Cast<u8>();
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} else if (config.scaling == config.ScaleXY) {
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Math::Vec4<u8> pixel1 =
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DecodePixel(config.input_format, src_pixel + 1 * src_bytes_per_pixel);
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Math::Vec4<u8> pixel2 =
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DecodePixel(config.input_format, src_pixel + 2 * src_bytes_per_pixel);
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Math::Vec4<u8> pixel3 =
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DecodePixel(config.input_format, src_pixel + 3 * src_bytes_per_pixel);
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src_color = (((src_color + pixel1) + (pixel2 + pixel3)) / 4).Cast<u8>();
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}
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u8* dst_pixel = dst_pointer + dst_offset;
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switch (config.output_format) {
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case Regs::PixelFormat::RGBA8:
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Color::EncodeRGBA8(src_color, dst_pixel);
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break;
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case Regs::PixelFormat::RGB8:
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Color::EncodeRGB8(src_color, dst_pixel);
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break;
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case Regs::PixelFormat::RGB565:
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Color::EncodeRGB565(src_color, dst_pixel);
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break;
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case Regs::PixelFormat::RGB5A1:
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Color::EncodeRGB5A1(src_color, dst_pixel);
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break;
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case Regs::PixelFormat::RGBA4:
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Color::EncodeRGBA4(src_color, dst_pixel);
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break;
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default:
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LOG_ERROR(HW_GPU, "Unknown destination framebuffer format %x",
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config.output_format.Value());
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break;
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}
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}
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}
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}
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static void TextureCopy(const Regs::DisplayTransferConfig& config) {
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const PAddr src_addr = config.GetPhysicalInputAddress();
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const PAddr dst_addr = config.GetPhysicalOutputAddress();
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// TODO: do hwtest with these cases
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if (!Memory::IsValidPhysicalAddress(src_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid input address 0x%08X", src_addr);
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return;
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}
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if (!Memory::IsValidPhysicalAddress(dst_addr)) {
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LOG_CRITICAL(HW_GPU, "invalid output address 0x%08X", dst_addr);
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return;
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}
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if (config.texture_copy.input_width == 0) {
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LOG_CRITICAL(HW_GPU, "zero input width");
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return;
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}
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if (config.texture_copy.output_width == 0) {
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LOG_CRITICAL(HW_GPU, "zero output width");
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return;
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}
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if (config.texture_copy.size == 0) {
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LOG_CRITICAL(HW_GPU, "zero size");
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return;
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}
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if (VideoCore::g_renderer->Rasterizer()->AccelerateTextureCopy(config))
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return;
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u8* src_pointer = Memory::GetPhysicalPointer(src_addr);
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u8* dst_pointer = Memory::GetPhysicalPointer(dst_addr);
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u32 input_width = config.texture_copy.input_width * 16;
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u32 input_gap = config.texture_copy.input_gap * 16;
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u32 output_width = config.texture_copy.output_width * 16;
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u32 output_gap = config.texture_copy.output_gap * 16;
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size_t contiguous_input_size =
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config.texture_copy.size / input_width * (input_width + input_gap);
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Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(),
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static_cast<u32>(contiguous_input_size));
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size_t contiguous_output_size =
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config.texture_copy.size / output_width * (output_width + output_gap);
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Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(),
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static_cast<u32>(contiguous_output_size));
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u32 remaining_size = config.texture_copy.size;
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u32 remaining_input = input_width;
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u32 remaining_output = output_width;
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while (remaining_size > 0) {
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u32 copy_size = std::min({remaining_input, remaining_output, remaining_size});
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std::memcpy(dst_pointer, src_pointer, copy_size);
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src_pointer += copy_size;
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dst_pointer += copy_size;
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remaining_input -= copy_size;
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remaining_output -= copy_size;
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remaining_size -= copy_size;
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if (remaining_input == 0) {
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remaining_input = input_width;
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src_pointer += input_gap;
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}
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if (remaining_output == 0) {
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remaining_output = output_width;
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dst_pointer += output_gap;
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}
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}
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}
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template <typename T>
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inline void Write(u32 addr, const T data) {
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addr -= HW::VADDR_GPU;
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u32 index = addr / 4;
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// Writes other than u32 are untested, so I'd rather have them abort than silently fail
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if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
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LOG_ERROR(HW_GPU, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
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return;
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}
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g_regs[index] = static_cast<u32>(data);
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switch (index) {
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// Memory fills are triggered once the fill value is written.
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3):
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3): {
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const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger));
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auto& config = g_regs.memory_fill_config[is_second_filler];
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if (config.trigger) {
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MemoryFill(config);
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LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(),
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config.GetEndAddress());
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// It seems that it won't signal interrupt if "address_start" is zero.
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// TODO: hwtest this
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if (config.GetStartAddress() != 0) {
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if (!is_second_filler) {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0);
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} else {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC1);
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}
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}
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// Reset "trigger" flag and set the "finish" flag
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// NOTE: This was confirmed to happen on hardware even if "address_start" is zero.
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config.trigger.Assign(0);
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config.finished.Assign(1);
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}
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break;
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}
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case GPU_REG_INDEX(display_transfer_config.trigger): {
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MICROPROFILE_SCOPE(GPU_DisplayTransfer);
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const auto& config = g_regs.display_transfer_config;
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if (config.trigger & 1) {
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if (Pica::g_debug_context)
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Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer,
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nullptr);
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if (config.is_texture_copy) {
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TextureCopy(config);
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LOG_TRACE(HW_GPU, "TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> "
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"0x%08X(%u+%u), flags 0x%08X",
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config.texture_copy.size, config.GetPhysicalInputAddress(),
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config.texture_copy.input_width * 16, config.texture_copy.input_gap * 16,
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config.GetPhysicalOutputAddress(), config.texture_copy.output_width * 16,
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config.texture_copy.output_gap * 16, config.flags);
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} else {
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DisplayTransfer(config);
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LOG_TRACE(HW_GPU, "DisplayTransfer: 0x%08x(%ux%u)-> "
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"0x%08x(%ux%u), dst format %x, flags 0x%08X",
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config.GetPhysicalInputAddress(), config.input_width.Value(),
|
|
config.input_height.Value(), config.GetPhysicalOutputAddress(),
|
|
config.output_width.Value(), config.output_height.Value(),
|
|
config.output_format.Value(), config.flags);
|
|
}
|
|
|
|
g_regs.display_transfer_config.trigger = 0;
|
|
GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF);
|
|
}
|
|
break;
|
|
}
|
|
|
|
// Seems like writing to this register triggers processing
|
|
case GPU_REG_INDEX(command_processor_config.trigger): {
|
|
const auto& config = g_regs.command_processor_config;
|
|
if (config.trigger & 1) {
|
|
MICROPROFILE_SCOPE(GPU_CmdlistProcessing);
|
|
|
|
u32* buffer = (u32*)Memory::GetPhysicalPointer(config.GetPhysicalAddress());
|
|
|
|
if (Pica::g_debug_context && Pica::g_debug_context->recorder) {
|
|
Pica::g_debug_context->recorder->MemoryAccessed((u8*)buffer, config.size,
|
|
config.GetPhysicalAddress());
|
|
}
|
|
|
|
Pica::CommandProcessor::ProcessCommandList(buffer, config.size);
|
|
|
|
g_regs.command_processor_config.trigger = 0;
|
|
}
|
|
break;
|
|
}
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
// Notify tracer about the register write
|
|
// This is happening *after* handling the write to make sure we properly catch all memory reads.
|
|
if (Pica::g_debug_context && Pica::g_debug_context->recorder) {
|
|
// addr + GPU VBase - IO VBase + IO PBase
|
|
Pica::g_debug_context->recorder->RegisterWritten<T>(
|
|
addr + 0x1EF00000 - 0x1EC00000 + 0x10100000, data);
|
|
}
|
|
}
|
|
|
|
// Explicitly instantiate template functions because we aren't defining this in the header:
|
|
|
|
template void Read<u64>(u64& var, const u32 addr);
|
|
template void Read<u32>(u32& var, const u32 addr);
|
|
template void Read<u16>(u16& var, const u32 addr);
|
|
template void Read<u8>(u8& var, const u32 addr);
|
|
|
|
template void Write<u64>(u32 addr, const u64 data);
|
|
template void Write<u32>(u32 addr, const u32 data);
|
|
template void Write<u16>(u32 addr, const u16 data);
|
|
template void Write<u8>(u32 addr, const u8 data);
|
|
|
|
static void FrameLimiter() {
|
|
time_delay += FIXED_FRAME_TIME;
|
|
time_delay = MathUtil::Clamp(time_delay, -MAX_LAG_TIME, MAX_LAG_TIME);
|
|
s32 desired_time = static_cast<s32>(time_delay);
|
|
s32 elapsed_time = static_cast<s32>(Common::Timer::GetTimeMs() - time_point);
|
|
|
|
if (elapsed_time < desired_time) {
|
|
Common::SleepCurrentThread(desired_time - elapsed_time);
|
|
}
|
|
|
|
u32 frame_time = Common::Timer::GetTimeMs() - time_point;
|
|
|
|
time_delay -= frame_time;
|
|
}
|
|
|
|
/// Update hardware
|
|
static void VBlankCallback(u64 userdata, int cycles_late) {
|
|
frame_count++;
|
|
VideoCore::g_renderer->SwapBuffers();
|
|
|
|
// Signal to GSP that GPU interrupt has occurred
|
|
// TODO(yuriks): hwtest to determine if PDC0 is for the Top screen and PDC1 for the Sub
|
|
// screen, or if both use the same interrupts and these two instead determine the
|
|
// beginning and end of the VBlank period. If needed, split the interrupt firing into
|
|
// two different intervals.
|
|
GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PDC0);
|
|
GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PDC1);
|
|
|
|
// Check for user input updates
|
|
Service::HID::Update();
|
|
|
|
if (!Settings::values.use_vsync && Settings::values.toggle_framelimit) {
|
|
FrameLimiter();
|
|
}
|
|
|
|
time_point = Common::Timer::GetTimeMs();
|
|
|
|
// Reschedule recurrent event
|
|
CoreTiming::ScheduleEvent(frame_ticks - cycles_late, vblank_event);
|
|
}
|
|
|
|
/// Initialize hardware
|
|
void Init() {
|
|
memset(&g_regs, 0, sizeof(g_regs));
|
|
|
|
auto& framebuffer_top = g_regs.framebuffer_config[0];
|
|
auto& framebuffer_sub = g_regs.framebuffer_config[1];
|
|
|
|
// Setup default framebuffer addresses (located in VRAM)
|
|
// .. or at least these are the ones used by system applets.
|
|
// There's probably a smarter way to come up with addresses
|
|
// like this which does not require hardcoding.
|
|
framebuffer_top.address_left1 = 0x181E6000;
|
|
framebuffer_top.address_left2 = 0x1822C800;
|
|
framebuffer_top.address_right1 = 0x18273000;
|
|
framebuffer_top.address_right2 = 0x182B9800;
|
|
framebuffer_sub.address_left1 = 0x1848F000;
|
|
framebuffer_sub.address_left2 = 0x184C7800;
|
|
|
|
framebuffer_top.width.Assign(240);
|
|
framebuffer_top.height.Assign(400);
|
|
framebuffer_top.stride = 3 * 240;
|
|
framebuffer_top.color_format.Assign(Regs::PixelFormat::RGB8);
|
|
framebuffer_top.active_fb = 0;
|
|
|
|
framebuffer_sub.width.Assign(240);
|
|
framebuffer_sub.height.Assign(320);
|
|
framebuffer_sub.stride = 3 * 240;
|
|
framebuffer_sub.color_format.Assign(Regs::PixelFormat::RGB8);
|
|
framebuffer_sub.active_fb = 0;
|
|
|
|
frame_count = 0;
|
|
time_point = Common::Timer::GetTimeMs();
|
|
|
|
vblank_event = CoreTiming::RegisterEvent("GPU::VBlankCallback", VBlankCallback);
|
|
CoreTiming::ScheduleEvent(frame_ticks, vblank_event);
|
|
|
|
LOG_DEBUG(HW_GPU, "initialized OK");
|
|
}
|
|
|
|
/// Shutdown hardware
|
|
void Shutdown() {
|
|
LOG_DEBUG(HW_GPU, "shutdown OK");
|
|
}
|
|
|
|
} // namespace
|