130 lines
3.4 KiB
C++
130 lines
3.4 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cstring>
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#include "common/make_unique.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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#include "core/arm/dyncom/arm_dyncom.h"
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#include "core/arm/dyncom/arm_dyncom_interpreter.h"
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#include "core/arm/dyncom/arm_dyncom_run.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
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state = Common::make_unique<ARMul_State>();
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ARMul_NewState(state.get());
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ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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state->abort_model = ABORT_BASE_RESTORED;
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state->bigendSig = LOW;
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state->lateabtSig = LOW;
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state->NirqSig = HIGH;
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// Reset the core to initial state
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ARMul_Reset(state.get());
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state->Emulate = RUN;
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// Switch to the desired privilege mode.
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switch_mode(state.get(), initial_mode);
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state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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state->Reg[15] = 0x00000000;
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}
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ARM_DynCom::~ARM_DynCom() {
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}
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void ARM_DynCom::SetPC(u32 pc) {
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state->Reg[15] = pc;
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}
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u32 ARM_DynCom::GetPC() const {
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return state->Reg[15];
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}
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u32 ARM_DynCom::GetReg(int index) const {
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return state->Reg[index];
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}
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void ARM_DynCom::SetReg(int index, u32 value) {
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state->Reg[index] = value;
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}
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u32 ARM_DynCom::GetCPSR() const {
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return state->Cpsr;
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}
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void ARM_DynCom::SetCPSR(u32 cpsr) {
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state->Cpsr = cpsr;
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}
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u32 ARM_DynCom::GetCP15Register(CP15Register reg) {
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return state->CP15[reg];
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}
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void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
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state->CP15[reg] = value;
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}
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void ARM_DynCom::AddTicks(u64 ticks) {
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down_count -= ticks;
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if (down_count < 0)
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CoreTiming::Advance();
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}
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void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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state->NumInstrsToExecute = num_instructions;
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// Dyncom only breaks on instruction dispatch. This only happens on every instruction when
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// executing one instruction at a time. Otherwise, if a block is being executed, more
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// instructions may actually be executed than specified.
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unsigned ticks_executed = InterpreterMainLoop(state.get());
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AddTicks(ticks_executed);
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}
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void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg) {
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memset(&context, 0, sizeof(Core::ThreadContext));
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context.cpu_registers[0] = arg;
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context.pc = entry_point;
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context.sp = stack_top;
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context.cpsr = 0x1F; // Usermode
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}
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void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
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ctx.sp = state->Reg[13];
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ctx.lr = state->Reg[14];
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ctx.pc = state->Reg[15];
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ctx.cpsr = state->Cpsr;
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ctx.fpscr = state->VFP[1];
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ctx.fpexc = state->VFP[2];
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}
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void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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state->Reg[13] = ctx.sp;
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state->Reg[14] = ctx.lr;
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state->Reg[15] = ctx.pc;
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state->Cpsr = ctx.cpsr;
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state->VFP[1] = ctx.fpscr;
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state->VFP[2] = ctx.fpexc;
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}
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void ARM_DynCom::PrepareReschedule() {
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state->NumInstrsToExecute = 0;
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}
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