249 lines
7.1 KiB
C++
249 lines
7.1 KiB
C++
/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#pragma once
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#include <array>
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#include <unordered_map>
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#include "common/common_types.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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// Signal levels
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enum { LOW = 0, HIGH = 1, LOWHIGH = 1, HIGHLOW = 2 };
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// Cache types
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enum {
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NONCACHE = 0,
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DATACACHE = 1,
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INSTCACHE = 2,
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};
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// ARM privilege modes
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enum PrivilegeMode {
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USER32MODE = 16,
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FIQ32MODE = 17,
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IRQ32MODE = 18,
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SVC32MODE = 19,
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ABORT32MODE = 23,
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UNDEF32MODE = 27,
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SYSTEM32MODE = 31
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};
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// ARM privilege mode register banks
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enum {
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USERBANK = 0,
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FIQBANK = 1,
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IRQBANK = 2,
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SVCBANK = 3,
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ABORTBANK = 4,
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UNDEFBANK = 5,
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DUMMYBANK = 6,
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SYSTEMBANK = 7
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};
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// Hardware vector addresses
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enum {
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ARMResetV = 0,
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ARMUndefinedInstrV = 4,
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ARMSWIV = 8,
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ARMPrefetchAbortV = 12,
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ARMDataAbortV = 16,
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ARMAddrExceptnV = 20,
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ARMIRQV = 24,
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ARMFIQV = 28,
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ARMErrorV = 32, // This is an offset, not an address!
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ARMul_ResetV = ARMResetV,
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ARMul_UndefinedInstrV = ARMUndefinedInstrV,
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ARMul_SWIV = ARMSWIV,
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ARMul_PrefetchAbortV = ARMPrefetchAbortV,
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ARMul_DataAbortV = ARMDataAbortV,
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ARMul_AddrExceptnV = ARMAddrExceptnV,
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ARMul_IRQV = ARMIRQV,
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ARMul_FIQV = ARMFIQV
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};
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// Coprocessor status values
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enum {
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ARMul_FIRST = 0,
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ARMul_TRANSFER = 1,
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ARMul_BUSY = 2,
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ARMul_DATA = 3,
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ARMul_INTERRUPT = 4,
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ARMul_DONE = 0,
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ARMul_CANT = 1,
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ARMul_INC = 3
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};
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// Instruction condition codes
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enum ConditionCode {
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EQ = 0,
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NE = 1,
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CS = 2,
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CC = 3,
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MI = 4,
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PL = 5,
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VS = 6,
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VC = 7,
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HI = 8,
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LS = 9,
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GE = 10,
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LT = 11,
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GT = 12,
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LE = 13,
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AL = 14,
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NV = 15,
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};
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// Flags for use with the APSR.
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enum : u32 {
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NBIT = (1U << 31U),
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ZBIT = (1 << 30),
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CBIT = (1 << 29),
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VBIT = (1 << 28),
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QBIT = (1 << 27),
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JBIT = (1 << 24),
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EBIT = (1 << 9),
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ABIT = (1 << 8),
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IBIT = (1 << 7),
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FBIT = (1 << 6),
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TBIT = (1 << 5),
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// Masks for groups of bits in the APSR.
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MODEBITS = 0x1F,
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INTBITS = 0x1C0,
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};
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// Values for Emulate.
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enum {
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STOP = 0, // Stop
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CHANGEMODE = 1, // Change mode
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ONCE = 2, // Execute just one iteration
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RUN = 3 // Continuous execution
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};
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struct ARMul_State final {
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public:
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explicit ARMul_State(PrivilegeMode initial_mode);
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void ChangePrivilegeMode(u32 new_mode);
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void Reset();
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// Reads/writes data in big/little endian format based on the
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// state of the E (endian) bit in the APSR.
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u8 ReadMemory8(u32 address) const;
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u16 ReadMemory16(u32 address) const;
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u32 ReadMemory32(u32 address) const;
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u64 ReadMemory64(u32 address) const;
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void WriteMemory8(u32 address, u8 data);
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void WriteMemory16(u32 address, u16 data);
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void WriteMemory32(u32 address, u32 data);
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void WriteMemory64(u32 address, u64 data);
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u32 ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const;
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void WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
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// Exclusive memory access functions
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bool IsExclusiveMemoryAccess(u32 address) const {
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return exclusive_state && exclusive_tag == (address & RESERVATION_GRANULE_MASK);
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}
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void SetExclusiveMemoryAddress(u32 address) {
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exclusive_tag = address & RESERVATION_GRANULE_MASK;
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exclusive_state = true;
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}
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void UnsetExclusiveMemoryAddress() {
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exclusive_tag = 0xFFFFFFFF;
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exclusive_state = false;
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}
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// Whether or not the given CPU is in big endian mode (E bit is set)
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bool InBigEndianMode() const {
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return (Cpsr & (1 << 9)) != 0;
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}
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// Whether or not the given CPU is in a mode other than user mode.
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bool InAPrivilegedMode() const {
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return (Mode != USER32MODE);
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}
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// Whether or not the current CPU mode has a Saved Program Status Register
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bool CurrentModeHasSPSR() const {
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return Mode != SYSTEM32MODE && InAPrivilegedMode();
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}
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// Note that for the 3DS, a Thumb instruction will only ever be
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// two bytes in size. Thus we don't need to worry about ThumbEE
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// or Thumb-2 where instructions can be 4 bytes in length.
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u32 GetInstructionSize() const {
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return TFlag ? 2 : 4;
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}
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std::array<u32, 16> Reg{}; // The current register file
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std::array<u32, 2> Reg_usr{};
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std::array<u32, 2> Reg_svc{}; // R13_SVC R14_SVC
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std::array<u32, 2> Reg_abort{}; // R13_ABORT R14_ABORT
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std::array<u32, 2> Reg_undef{}; // R13 UNDEF R14 UNDEF
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std::array<u32, 2> Reg_irq{}; // R13_IRQ R14_IRQ
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std::array<u32, 7> Reg_firq{}; // R8---R14 FIRQ
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std::array<u32, 7> Spsr{}; // The exception psr's
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std::array<u32, CP15_REGISTER_COUNT> CP15{};
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// FPSID, FPSCR, and FPEXC
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std::array<u32, VFP_SYSTEM_REGISTER_COUNT> VFP{};
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// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
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// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
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// and only 32 singleword registers are accessible (S0-S31).
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std::array<u32, 64> ExtReg{};
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u32 Emulate; // To start and stop emulation
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u32 Cpsr; // The current PSR
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u32 Spsr_copy;
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u32 phys_pc;
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u32 Mode; // The current mode
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u32 Bank; // The current register bank
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u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
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unsigned int shifter_carry_out;
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u32 TFlag; // Thumb state
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unsigned long long NumInstrs; // The number of instructions executed
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unsigned NumInstrsToExecute;
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unsigned NresetSig; // Reset the processor
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unsigned NfiqSig;
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unsigned NirqSig;
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unsigned abortSig;
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unsigned NtransSig;
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unsigned bigendSig;
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unsigned syscallSig;
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// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
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// process for our purposes), not per ARMul_State (which tracks CPU core state).
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std::unordered_map<u32, std::size_t> instruction_cache;
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private:
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void ResetMPCoreCP15Registers();
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// Defines a reservation granule of 2 words, which protects the first 2 words starting at the
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// tag. This is the smallest granule allowed by the v7 spec, and is coincidentally just large
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// enough to support LDR/STREXD.
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static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
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u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode
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bool exclusive_state;
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};
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