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Interpreter: Implement UMAAL
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1 changed files with 25 additions and 0 deletions
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@ -1034,6 +1034,29 @@ static uint32_t HandlerSmulxx(CPUContext& ctx, ARM::ARMInstr instr) {
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return NextInstr(ctx);
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}
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// Unsigned Multiply Accumulate Accumulate Long
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static uint32_t HandlerUmaal(CPUContext& ctx, ARM::ARMInstr instr) {
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if (!EvalCond(ctx, instr.cond))
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return NextInstr(ctx);
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// If either of the destination registers are PC, abort - this is unpredictable behavior!
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if (instr.idx_rm == 15 || instr.idx_rs == 15 || instr.idx_rd == 15 || instr.idx_rn == 15)
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return HandlerStubAnnotated(ctx, instr, __LINE__);
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// If the destination registers are equal, abort - this is unpredictable behavior!
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if (instr.idx_rd == instr.idx_rn)
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return HandlerStubAnnotated(ctx, instr, __LINE__);
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// First compute the result using the original register values, then write it back
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uint64_t result = static_cast<uint64_t>(ctx.cpu.FetchReg(instr.idx_rs)) * static_cast<uint64_t>(ctx.cpu.FetchReg(instr.idx_rm));
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result += ctx.cpu.reg[instr.idx_rd];
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result += ctx.cpu.reg[instr.idx_rn];
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ctx.cpu.reg[instr.idx_rd] = result & 0xFFFFFFFF;
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ctx.cpu.reg[instr.idx_rn] = result >> 32;
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return NextInstr(ctx);
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}
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// Signed Multiply Long
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static uint32_t HandlerSmull(CPUContext& ctx, ARM::ARMInstr instr) {
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if (!EvalCond(ctx, instr.cond))
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@ -1177,6 +1200,8 @@ static uint32_t HandlerUmlal(CPUContext& ctx, ARM::ARMInstr instr) {
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static uint32_t Handler00x0(InterpreterExecutionContext& ctx, ARM::ARMInstr instr) {
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if ((instr.raw & 0b1111'1110'0000'0000'0000'1111'0000) == 0b0000'0010'0000'0000'0000'1001'0000) {
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return HandlerMla(ctx, instr);
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} else if ((instr.raw & 0b1111'1111'0000'0000'0000'1111'0000) == 0b0000'0100'0000'0000'0000'1001'0000) {
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return HandlerUmaal(ctx, instr);
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} else if ((instr.raw & 0b1111'1110'0000'0000'0000'1111'0000) == 0b0000'1100'0000'0000'0000'1001'0000) {
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return HandlerSmull(ctx, instr);
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} else if ((instr.raw & 0b1111'1110'0000'0000'0000'1111'0000) == 0b0000'1110'0000'0000'0000'1001'0000) {
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