356 lines
17 KiB
C
Executable file
356 lines
17 KiB
C
Executable file
/*
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* Copyright (c) 2012
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* MIPS Technologies, Inc., California.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Author: Branimir Vasic (bvasic@mips.com)
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* Author: Zoran Lukic (zoranl@mips.com)
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* @file
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* Reference: libavutil/float_dsp.c
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*/
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#include "config.h"
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#include "libavutil/float_dsp.h"
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#include "libavutil/mips/asmdefs.h"
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#if HAVE_INLINE_ASM && HAVE_MIPSFPU
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#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
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static void vector_fmul_mips(float *dst, const float *src0, const float *src1,
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int len)
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{
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int i;
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if (len & 3) {
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for (i = 0; i < len; i++)
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dst[i] = src0[i] * src1[i];
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} else {
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float *d = (float *)dst;
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float *d_end = d + len;
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float *s0 = (float *)src0;
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float *s1 = (float *)src1;
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float src0_0, src0_1, src0_2, src0_3;
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float src1_0, src1_1, src1_2, src1_3;
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__asm__ volatile (
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"1: \n\t"
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"lwc1 %[src0_0], 0(%[s0]) \n\t"
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"lwc1 %[src1_0], 0(%[s1]) \n\t"
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"lwc1 %[src0_1], 4(%[s0]) \n\t"
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"lwc1 %[src1_1], 4(%[s1]) \n\t"
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"lwc1 %[src0_2], 8(%[s0]) \n\t"
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"lwc1 %[src1_2], 8(%[s1]) \n\t"
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"lwc1 %[src0_3], 12(%[s0]) \n\t"
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"lwc1 %[src1_3], 12(%[s1]) \n\t"
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"mul.s %[src0_0], %[src0_0], %[src1_0] \n\t"
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"mul.s %[src0_1], %[src0_1], %[src1_1] \n\t"
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"mul.s %[src0_2], %[src0_2], %[src1_2] \n\t"
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"mul.s %[src0_3], %[src0_3], %[src1_3] \n\t"
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"swc1 %[src0_0], 0(%[d]) \n\t"
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"swc1 %[src0_1], 4(%[d]) \n\t"
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"swc1 %[src0_2], 8(%[d]) \n\t"
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"swc1 %[src0_3], 12(%[d]) \n\t"
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PTR_ADDIU "%[s0], %[s0], 16 \n\t"
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PTR_ADDIU "%[s1], %[s1], 16 \n\t"
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PTR_ADDIU "%[d], %[d], 16 \n\t"
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"bne %[d], %[d_end], 1b \n\t"
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: [src0_0]"=&f"(src0_0), [src0_1]"=&f"(src0_1),
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[src0_2]"=&f"(src0_2), [src0_3]"=&f"(src0_3),
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[src1_0]"=&f"(src1_0), [src1_1]"=&f"(src1_1),
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[src1_2]"=&f"(src1_2), [src1_3]"=&f"(src1_3),
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[d]"+r"(d), [s0]"+r"(s0), [s1]"+r"(s1)
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: [d_end]"r"(d_end)
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: "memory"
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);
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}
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}
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static void vector_fmul_scalar_mips(float *dst, const float *src, float mul,
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int len)
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{
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float temp0, temp1, temp2, temp3;
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float *local_src = (float*)src;
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float *end = local_src + len;
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/* loop unrolled 4 times */
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__asm__ volatile(
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".set push \n\t"
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".set noreorder \n\t"
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"1: \n\t"
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"lwc1 %[temp0], 0(%[src]) \n\t"
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"lwc1 %[temp1], 4(%[src]) \n\t"
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"lwc1 %[temp2], 8(%[src]) \n\t"
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"lwc1 %[temp3], 12(%[src]) \n\t"
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PTR_ADDIU "%[dst], %[dst], 16 \n\t"
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"mul.s %[temp0], %[temp0], %[mul] \n\t"
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"mul.s %[temp1], %[temp1], %[mul] \n\t"
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"mul.s %[temp2], %[temp2], %[mul] \n\t"
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"mul.s %[temp3], %[temp3], %[mul] \n\t"
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PTR_ADDIU "%[src], %[src], 16 \n\t"
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"swc1 %[temp0], -16(%[dst]) \n\t"
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"swc1 %[temp1], -12(%[dst]) \n\t"
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"swc1 %[temp2], -8(%[dst]) \n\t"
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"bne %[src], %[end], 1b \n\t"
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" swc1 %[temp3], -4(%[dst]) \n\t"
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".set pop \n\t"
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: [temp0]"=&f"(temp0), [temp1]"=&f"(temp1),
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[temp2]"=&f"(temp2), [temp3]"=&f"(temp3),
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[dst]"+r"(dst), [src]"+r"(local_src)
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: [end]"r"(end), [mul]"f"(mul)
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: "memory"
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);
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}
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static void vector_fmul_window_mips(float *dst, const float *src0,
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const float *src1, const float *win, int len)
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{
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float * dst_j, *win_j, *src0_i, *src1_j, *dst_i, *win_i;
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float temp, temp1, temp2, temp3;
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float s0, s01, s1, s11;
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float wi, wi1, wi2, wi3;
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float wj, wj1, wj2, wj3;
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const float * lp_end = win + len;
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win_i = (float *)win;
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win_j = (float *)(win + 2 * len -1);
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src1_j = (float *)(src1 + len - 1);
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src0_i = (float *)src0;
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dst_i = (float *)dst;
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dst_j = (float *)(dst + 2 * len -1);
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/* loop unrolled 4 times */
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__asm__ volatile (
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"1:"
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"lwc1 %[s1], 0(%[src1_j]) \n\t"
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"lwc1 %[wi], 0(%[win_i]) \n\t"
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"lwc1 %[wj], 0(%[win_j]) \n\t"
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"lwc1 %[s11], -4(%[src1_j]) \n\t"
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"lwc1 %[wi1], 4(%[win_i]) \n\t"
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"lwc1 %[wj1], -4(%[win_j]) \n\t"
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"lwc1 %[s0], 0(%[src0_i]) \n\t"
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"lwc1 %[s01], 4(%[src0_i]) \n\t"
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"mul.s %[temp], %[s1], %[wi] \n\t"
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"mul.s %[temp1], %[s1], %[wj] \n\t"
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"mul.s %[temp2], %[s11], %[wi1] \n\t"
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"mul.s %[temp3], %[s11], %[wj1] \n\t"
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"lwc1 %[s1], -8(%[src1_j]) \n\t"
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"lwc1 %[wi2], 8(%[win_i]) \n\t"
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"lwc1 %[wj2], -8(%[win_j]) \n\t"
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"lwc1 %[s11], -12(%[src1_j]) \n\t"
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"msub.s %[temp], %[temp], %[s0], %[wj] \n\t"
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"madd.s %[temp1], %[temp1], %[s0], %[wi] \n\t"
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"msub.s %[temp2], %[temp2], %[s01], %[wj1] \n\t"
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"madd.s %[temp3], %[temp3], %[s01], %[wi1] \n\t"
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"lwc1 %[wi3], 12(%[win_i]) \n\t"
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"lwc1 %[wj3], -12(%[win_j]) \n\t"
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"lwc1 %[s0], 8(%[src0_i]) \n\t"
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"lwc1 %[s01], 12(%[src0_i]) \n\t"
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PTR_ADDIU "%[src1_j],-16 \n\t"
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PTR_ADDIU "%[win_i],16 \n\t"
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PTR_ADDIU "%[win_j],-16 \n\t"
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PTR_ADDIU "%[src0_i],16 \n\t"
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"swc1 %[temp], 0(%[dst_i]) \n\t" /* dst[i] = s0*wj - s1*wi; */
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"swc1 %[temp1], 0(%[dst_j]) \n\t" /* dst[j] = s0*wi + s1*wj; */
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"swc1 %[temp2], 4(%[dst_i]) \n\t" /* dst[i+1] = s01*wj1 - s11*wi1; */
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"swc1 %[temp3], -4(%[dst_j]) \n\t" /* dst[j-1] = s01*wi1 + s11*wj1; */
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"mul.s %[temp], %[s1], %[wi2] \n\t"
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"mul.s %[temp1], %[s1], %[wj2] \n\t"
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"mul.s %[temp2], %[s11], %[wi3] \n\t"
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"mul.s %[temp3], %[s11], %[wj3] \n\t"
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"msub.s %[temp], %[temp], %[s0], %[wj2] \n\t"
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"madd.s %[temp1], %[temp1], %[s0], %[wi2] \n\t"
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"msub.s %[temp2], %[temp2], %[s01], %[wj3] \n\t"
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"madd.s %[temp3], %[temp3], %[s01], %[wi3] \n\t"
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"swc1 %[temp], 8(%[dst_i]) \n\t" /* dst[i+2] = s0*wj2 - s1*wi2; */
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"swc1 %[temp1], -8(%[dst_j]) \n\t" /* dst[j-2] = s0*wi2 + s1*wj2; */
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"swc1 %[temp2], 12(%[dst_i]) \n\t" /* dst[i+2] = s01*wj3 - s11*wi3; */
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"swc1 %[temp3], -12(%[dst_j]) \n\t" /* dst[j-3] = s01*wi3 + s11*wj3; */
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PTR_ADDIU "%[dst_i],16 \n\t"
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PTR_ADDIU "%[dst_j],-16 \n\t"
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"bne %[win_i], %[lp_end], 1b \n\t"
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: [temp]"=&f"(temp), [temp1]"=&f"(temp1), [temp2]"=&f"(temp2),
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[temp3]"=&f"(temp3), [src0_i]"+r"(src0_i), [win_i]"+r"(win_i),
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[src1_j]"+r"(src1_j), [win_j]"+r"(win_j), [dst_i]"+r"(dst_i),
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[dst_j]"+r"(dst_j), [s0] "=&f"(s0), [s01]"=&f"(s01), [s1] "=&f"(s1),
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[s11]"=&f"(s11), [wi] "=&f"(wi), [wj] "=&f"(wj), [wi2]"=&f"(wi2),
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[wj2]"=&f"(wj2), [wi3]"=&f"(wi3), [wj3]"=&f"(wj3), [wi1]"=&f"(wi1),
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[wj1]"=&f"(wj1)
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: [lp_end]"r"(lp_end)
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: "memory"
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);
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}
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static void butterflies_float_mips(float *av_restrict v1, float *av_restrict v2,
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int len)
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{
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float temp0, temp1, temp2, temp3, temp4;
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float temp5, temp6, temp7, temp8, temp9;
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float temp10, temp11, temp12, temp13, temp14, temp15;
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int pom;
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pom = (len >> 2)-1;
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/* loop unrolled 4 times */
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__asm__ volatile (
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"lwc1 %[temp0], 0(%[v1]) \n\t"
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"lwc1 %[temp1], 4(%[v1]) \n\t"
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"lwc1 %[temp2], 8(%[v1]) \n\t"
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"lwc1 %[temp3], 12(%[v1]) \n\t"
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"lwc1 %[temp4], 0(%[v2]) \n\t"
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"lwc1 %[temp5], 4(%[v2]) \n\t"
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"lwc1 %[temp6], 8(%[v2]) \n\t"
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"lwc1 %[temp7], 12(%[v2]) \n\t"
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"beq %[pom], $zero, 2f \n\t"
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"1: \n\t"
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"sub.s %[temp8], %[temp0], %[temp4] \n\t"
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"add.s %[temp9], %[temp0], %[temp4] \n\t"
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"sub.s %[temp10], %[temp1], %[temp5] \n\t"
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"add.s %[temp11], %[temp1], %[temp5] \n\t"
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"sub.s %[temp12], %[temp2], %[temp6] \n\t"
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"add.s %[temp13], %[temp2], %[temp6] \n\t"
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"sub.s %[temp14], %[temp3], %[temp7] \n\t"
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"add.s %[temp15], %[temp3], %[temp7] \n\t"
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PTR_ADDIU "%[v1], %[v1], 16 \n\t"
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PTR_ADDIU "%[v2], %[v2], 16 \n\t"
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"addiu %[pom], %[pom], -1 \n\t"
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"lwc1 %[temp0], 0(%[v1]) \n\t"
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"lwc1 %[temp1], 4(%[v1]) \n\t"
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"lwc1 %[temp2], 8(%[v1]) \n\t"
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"lwc1 %[temp3], 12(%[v1]) \n\t"
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"lwc1 %[temp4], 0(%[v2]) \n\t"
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"lwc1 %[temp5], 4(%[v2]) \n\t"
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"lwc1 %[temp6], 8(%[v2]) \n\t"
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"lwc1 %[temp7], 12(%[v2]) \n\t"
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"swc1 %[temp9], -16(%[v1]) \n\t"
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"swc1 %[temp8], -16(%[v2]) \n\t"
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"swc1 %[temp11], -12(%[v1]) \n\t"
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"swc1 %[temp10], -12(%[v2]) \n\t"
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"swc1 %[temp13], -8(%[v1]) \n\t"
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"swc1 %[temp12], -8(%[v2]) \n\t"
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"swc1 %[temp15], -4(%[v1]) \n\t"
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"swc1 %[temp14], -4(%[v2]) \n\t"
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"bgtz %[pom], 1b \n\t"
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"2: \n\t"
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"sub.s %[temp8], %[temp0], %[temp4] \n\t"
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"add.s %[temp9], %[temp0], %[temp4] \n\t"
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"sub.s %[temp10], %[temp1], %[temp5] \n\t"
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"add.s %[temp11], %[temp1], %[temp5] \n\t"
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"sub.s %[temp12], %[temp2], %[temp6] \n\t"
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"add.s %[temp13], %[temp2], %[temp6] \n\t"
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"sub.s %[temp14], %[temp3], %[temp7] \n\t"
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"add.s %[temp15], %[temp3], %[temp7] \n\t"
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"swc1 %[temp9], 0(%[v1]) \n\t"
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"swc1 %[temp8], 0(%[v2]) \n\t"
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"swc1 %[temp11], 4(%[v1]) \n\t"
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"swc1 %[temp10], 4(%[v2]) \n\t"
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"swc1 %[temp13], 8(%[v1]) \n\t"
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"swc1 %[temp12], 8(%[v2]) \n\t"
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"swc1 %[temp15], 12(%[v1]) \n\t"
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"swc1 %[temp14], 12(%[v2]) \n\t"
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: [v1]"+r"(v1), [v2]"+r"(v2), [pom]"+r"(pom), [temp0] "=&f" (temp0),
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[temp1]"=&f"(temp1), [temp2]"=&f"(temp2), [temp3]"=&f"(temp3),
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[temp4]"=&f"(temp4), [temp5]"=&f"(temp5), [temp6]"=&f"(temp6),
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[temp7]"=&f"(temp7), [temp8]"=&f"(temp8), [temp9]"=&f"(temp9),
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[temp10]"=&f"(temp10), [temp11]"=&f"(temp11), [temp12]"=&f"(temp12),
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[temp13]"=&f"(temp13), [temp14]"=&f"(temp14), [temp15]"=&f"(temp15)
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:
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: "memory"
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);
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}
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static void vector_fmul_reverse_mips(float *dst, const float *src0, const float *src1, int len){
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int i;
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float temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7;
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src1 += len-1;
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for(i=0; i<(len>>2); i++)
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{
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/* loop unrolled 4 times */
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__asm__ volatile(
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"lwc1 %[temp0], 0(%[src0]) \n\t"
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"lwc1 %[temp1], 0(%[src1]) \n\t"
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"lwc1 %[temp2], 4(%[src0]) \n\t"
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"lwc1 %[temp3], -4(%[src1]) \n\t"
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"lwc1 %[temp4], 8(%[src0]) \n\t"
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"lwc1 %[temp5], -8(%[src1]) \n\t"
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"lwc1 %[temp6], 12(%[src0]) \n\t"
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"lwc1 %[temp7], -12(%[src1]) \n\t"
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"mul.s %[temp0], %[temp1], %[temp0] \n\t"
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"mul.s %[temp2], %[temp3], %[temp2] \n\t"
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"mul.s %[temp4], %[temp5], %[temp4] \n\t"
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"mul.s %[temp6], %[temp7], %[temp6] \n\t"
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PTR_ADDIU "%[src0], %[src0], 16 \n\t"
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PTR_ADDIU "%[src1], %[src1], -16 \n\t"
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PTR_ADDIU "%[dst], %[dst], 16 \n\t"
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"swc1 %[temp0], -16(%[dst]) \n\t"
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"swc1 %[temp2], -12(%[dst]) \n\t"
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"swc1 %[temp4], -8(%[dst]) \n\t"
|
|
"swc1 %[temp6], -4(%[dst]) \n\t"
|
|
|
|
: [dst]"+r"(dst), [src0]"+r"(src0), [src1]"+r"(src1),
|
|
[temp0]"=&f"(temp0), [temp1]"=&f"(temp1),[temp2]"=&f"(temp2),
|
|
[temp3]"=&f"(temp3), [temp4]"=&f"(temp4), [temp5]"=&f"(temp5),
|
|
[temp6]"=&f"(temp6), [temp7]"=&f"(temp7)
|
|
:
|
|
: "memory"
|
|
);
|
|
}
|
|
}
|
|
#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
|
|
#endif /* HAVE_INLINE_ASM && HAVE_MIPSFPU */
|
|
|
|
void ff_float_dsp_init_mips(AVFloatDSPContext *fdsp) {
|
|
#if HAVE_INLINE_ASM && HAVE_MIPSFPU
|
|
#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
|
|
fdsp->vector_fmul = vector_fmul_mips;
|
|
fdsp->vector_fmul_scalar = vector_fmul_scalar_mips;
|
|
fdsp->vector_fmul_window = vector_fmul_window_mips;
|
|
fdsp->butterflies_float = butterflies_float_mips;
|
|
fdsp->vector_fmul_reverse = vector_fmul_reverse_mips;
|
|
#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
|
|
#endif /* HAVE_INLINE_ASM && HAVE_MIPSFPU */
|
|
}
|