2019-01-23 00:49:31 +01:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2019-07-12 02:54:07 +02:00
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#include <bitset>
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2019-03-06 02:25:01 +01:00
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#include "common/assert.h"
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2019-01-23 00:49:31 +01:00
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#include "common/logging/log.h"
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2019-04-23 01:05:43 +02:00
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#include "core/core.h"
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2019-01-23 00:49:31 +01:00
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#include "video_core/engines/kepler_compute.h"
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2019-04-23 01:05:43 +02:00
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#include "video_core/engines/maxwell_3d.h"
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2019-11-18 22:35:21 +01:00
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#include "video_core/engines/shader_type.h"
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2019-01-23 00:49:31 +01:00
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#include "video_core/memory_manager.h"
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2019-04-23 01:05:43 +02:00
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/decoders.h"
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2019-01-23 00:49:31 +01:00
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namespace Tegra::Engines {
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2019-04-23 01:05:43 +02:00
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KeplerCompute::KeplerCompute(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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MemoryManager& memory_manager)
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager}, upload_state{
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memory_manager,
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regs.upload} {}
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2019-01-23 00:49:31 +01:00
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KeplerCompute::~KeplerCompute() = default;
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void KeplerCompute::CallMethod(const GPU::MethodCall& method_call) {
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ASSERT_MSG(method_call.method < Regs::NUM_REGS,
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"Invalid KeplerCompute register, increase the size of the Regs structure");
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regs.reg_array[method_call.method] = method_call.argument;
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switch (method_call.method) {
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2019-04-23 01:05:43 +02:00
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case KEPLER_COMPUTE_REG_INDEX(exec_upload): {
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upload_state.ProcessExec(regs.exec_upload.linear != 0);
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break;
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}
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case KEPLER_COMPUTE_REG_INDEX(data_upload): {
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2019-04-23 14:02:24 +02:00
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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2019-12-27 02:14:10 +01:00
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if (is_last_call) {
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system.GPU().Maxwell3D().OnMemoryWrite();
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}
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break;
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}
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case KEPLER_COMPUTE_REG_INDEX(launch):
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ProcessLaunch();
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2019-01-23 00:49:31 +01:00
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break;
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default:
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break;
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}
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}
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2019-10-20 09:03:33 +02:00
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Texture::FullTextureInfo KeplerCompute::GetTexture(std::size_t offset) const {
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2019-07-12 02:54:07 +02:00
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const std::bitset<8> cbuf_mask = launch_description.const_buffer_enable_mask.Value();
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ASSERT(cbuf_mask[regs.tex_cb_index]);
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const auto& texinfo = launch_description.const_buffer_config[regs.tex_cb_index];
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ASSERT(texinfo.Address() != 0);
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const GPUVAddr address = texinfo.Address() + offset * sizeof(Texture::TextureHandle);
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ASSERT(address < texinfo.Address() + texinfo.size);
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const Texture::TextureHandle tex_handle{memory_manager.Read<u32>(address)};
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return GetTextureInfo(tex_handle);
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}
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2019-10-20 09:03:33 +02:00
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Texture::FullTextureInfo KeplerCompute::GetTextureInfo(Texture::TextureHandle tex_handle) const {
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return Texture::FullTextureInfo{GetTICEntry(tex_handle.tic_id), GetTSCEntry(tex_handle.tsc_id)};
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}
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2019-09-23 20:02:02 +02:00
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u32 KeplerCompute::AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const {
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ASSERT(stage == ShaderType::Compute);
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const auto& buffer = launch_description.const_buffer_config[const_buffer];
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u32 result;
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std::memcpy(&result, memory_manager.GetPointer(buffer.Address() + offset), sizeof(u32));
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return result;
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}
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2019-09-25 15:53:18 +02:00
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SamplerDescriptor KeplerCompute::AccessBoundSampler(ShaderType stage, u64 offset) const {
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return AccessBindlessSampler(stage, regs.tex_cb_index, offset * sizeof(Texture::TextureHandle));
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}
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SamplerDescriptor KeplerCompute::AccessBindlessSampler(ShaderType stage, u64 const_buffer,
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u64 offset) const {
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ASSERT(stage == ShaderType::Compute);
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const auto& tex_info_buffer = launch_description.const_buffer_config[const_buffer];
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2019-10-01 02:55:25 +02:00
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const GPUVAddr tex_info_address = tex_info_buffer.Address() + offset;
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const Texture::TextureHandle tex_handle{memory_manager.Read<u32>(tex_info_address)};
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const Texture::FullTextureInfo tex_info = GetTextureInfo(tex_handle);
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SamplerDescriptor result = SamplerDescriptor::FromTicTexture(tex_info.tic.texture_type.Value());
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result.is_shadow.Assign(tex_info.tsc.depth_compare_enabled.Value());
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return result;
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}
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2020-01-03 21:16:29 +01:00
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VideoCore::GuestDriverProfile& KeplerCompute::AccessGuestDriverProfile() {
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return rasterizer.AccessGuestDriverProfile();
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}
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2020-01-08 15:28:29 +01:00
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const VideoCore::GuestDriverProfile& KeplerCompute::AccessGuestDriverProfile() const {
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return rasterizer.AccessGuestDriverProfile();
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}
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2019-04-23 01:05:43 +02:00
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void KeplerCompute::ProcessLaunch() {
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const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
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memory_manager.ReadBlockUnsafe(launch_desc_loc, &launch_description,
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LaunchParams::NUM_LAUNCH_PARAMETERS * sizeof(u32));
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2019-07-15 03:25:13 +02:00
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const GPUVAddr code_addr = regs.code_loc.Address() + launch_description.program_start;
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LOG_TRACE(HW_GPU, "Compute invocation launched at address 0x{:016x}", code_addr);
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rasterizer.DispatchCompute(code_addr);
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}
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2019-07-12 02:54:07 +02:00
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Texture::TICEntry KeplerCompute::GetTICEntry(u32 tic_index) const {
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const GPUVAddr tic_address_gpu{regs.tic.Address() + tic_index * sizeof(Texture::TICEntry)};
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Texture::TICEntry tic_entry;
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memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry));
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const auto r_type{tic_entry.r_type.Value()};
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const auto g_type{tic_entry.g_type.Value()};
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const auto b_type{tic_entry.b_type.Value()};
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const auto a_type{tic_entry.a_type.Value()};
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// TODO(Subv): Different data types for separate components are not supported
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DEBUG_ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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return tic_entry;
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}
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Texture::TSCEntry KeplerCompute::GetTSCEntry(u32 tsc_index) const {
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const GPUVAddr tsc_address_gpu{regs.tsc.Address() + tsc_index * sizeof(Texture::TSCEntry)};
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Texture::TSCEntry tsc_entry;
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memory_manager.ReadBlockUnsafe(tsc_address_gpu, &tsc_entry, sizeof(Texture::TSCEntry));
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return tsc_entry;
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}
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2019-01-23 00:49:31 +01:00
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} // namespace Tegra::Engines
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