2014-04-09 02:38:33 +02:00
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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2014-04-05 04:26:06 +02:00
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#include "arm_interpreter.h"
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const static cpu_config_t s_arm11_cpu_info = {
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"armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
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};
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ARM_Interpreter::ARM_Interpreter() {
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2014-04-09 02:38:33 +02:00
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m_state = new ARMul_State;
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2014-04-05 04:26:06 +02:00
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ARMul_EmulateInit();
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2014-04-09 02:38:33 +02:00
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ARMul_NewState(m_state);
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2014-04-05 04:26:06 +02:00
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2014-04-09 02:38:33 +02:00
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m_state->abort_model = 0;
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m_state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
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m_state->bigendSig = LOW;
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2014-04-05 04:26:06 +02:00
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2014-04-09 02:38:33 +02:00
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ARMul_SelectProcessor(m_state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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m_state->lateabtSig = LOW;
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mmu_init(m_state);
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2014-04-05 04:26:06 +02:00
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// Reset the core to initial state
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2014-04-09 02:38:33 +02:00
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ARMul_Reset(m_state);
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m_state->NextInstr = 0;
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m_state->Emulate = 3;
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2014-04-05 04:26:06 +02:00
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2014-04-09 02:38:33 +02:00
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m_state->pc = m_state->Reg[15] = 0x00000000;
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m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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2014-04-05 04:26:06 +02:00
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}
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void ARM_Interpreter::SetPC(u32 pc) {
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2014-04-09 02:38:33 +02:00
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m_state->pc = m_state->Reg[15] = pc;
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}
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u32 ARM_Interpreter::GetPC() const {
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return m_state->pc;
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2014-04-05 04:26:06 +02:00
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}
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2014-04-09 02:38:33 +02:00
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u32 ARM_Interpreter::GetReg(int index) const {
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return m_state->Reg[index];
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2014-04-05 04:26:06 +02:00
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}
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2014-04-09 02:38:33 +02:00
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u32 ARM_Interpreter::GetCPSR() const {
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return m_state->Cpsr;
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2014-04-05 04:26:06 +02:00
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}
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2014-04-09 02:38:33 +02:00
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u64 ARM_Interpreter::GetTicks() const {
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return ARMul_Time(m_state);
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2014-04-05 04:26:06 +02:00
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}
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ARM_Interpreter::~ARM_Interpreter() {
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2014-04-09 02:38:33 +02:00
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delete m_state;
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2014-04-05 04:26:06 +02:00
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}
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void ARM_Interpreter::ExecuteInstruction() {
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2014-04-09 02:38:33 +02:00
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m_state->step++;
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m_state->cycle++;
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m_state->EndCondition = 0;
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m_state->stop_simulator = 0;
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m_state->NextInstr = RESUME;
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m_state->last_pc = m_state->Reg[15];
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m_state->Reg[15] = ARMul_DoInstr(m_state);
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m_state->Cpsr = ((m_state->Cpsr & 0x0fffffdf) | (m_state->NFlag << 31) | (m_state->ZFlag << 30) |
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(m_state->CFlag << 29) | (m_state->VFlag << 28) | (m_state->TFlag << 5));
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m_state->NextInstr |= PRIMEPIPE; // Flush pipe
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2014-04-05 04:26:06 +02:00
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}
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