suyu/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp

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// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "shader_recompiler/backend/spirv/emit_spirv.h"
#include "shader_recompiler/frontend/ir/modifiers.h"
namespace Shader::Backend::SPIRV {
namespace {
Id Decorate(EmitContext& ctx, IR::Inst* inst, Id op) {
const auto flags{inst->Flags<IR::FpControl>()};
if (flags.no_contraction) {
ctx.Decorate(op, spv::Decoration::NoContraction);
}
switch (flags.rounding) {
case IR::FpRounding::RN:
break;
case IR::FpRounding::RM:
ctx.Decorate(op, spv::Decoration::FPRoundingMode, spv::FPRoundingMode::RTN);
break;
case IR::FpRounding::RP:
ctx.Decorate(op, spv::Decoration::FPRoundingMode, spv::FPRoundingMode::RTP);
break;
case IR::FpRounding::RZ:
ctx.Decorate(op, spv::Decoration::FPRoundingMode, spv::FPRoundingMode::RTZ);
break;
}
if (flags.fmz_mode != IR::FmzMode::FTZ) {
throw NotImplementedException("Denorm management not implemented");
}
return op;
}
} // Anonymous namespace
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void EmitFPAbs16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPAbs32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPAbs64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFAdd(ctx.F16[1], a, b));
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}
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Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFAdd(ctx.F32[1], a, b));
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}
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Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFAdd(ctx.F64[1], a, b));
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}
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Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
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return Decorate(ctx, inst, ctx.OpFma(ctx.F16[1], a, b, c));
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}
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Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
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return Decorate(ctx, inst, ctx.OpFma(ctx.F32[1], a, b, c));
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}
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Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
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return Decorate(ctx, inst, ctx.OpFma(ctx.F64[1], a, b, c));
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}
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void EmitFPMax32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPMax64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPMin32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPMin64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFMul(ctx.F16[1], a, b));
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}
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Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFMul(ctx.F32[1], a, b));
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}
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Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFMul(ctx.F64[1], a, b));
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}
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void EmitFPNeg16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPNeg32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPNeg64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPRecip32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPRecip64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPRecipSqrt32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPRecipSqrt64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPSqrt(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPSin(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPSinNotReduced(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPExp2(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPExp2NotReduced(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPCos(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPCosNotReduced(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPLog2(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPSaturate16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPSaturate32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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void EmitFPSaturate64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
}
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Id EmitFPRoundEven16(EmitContext& ctx, Id value) {
return ctx.OpRoundEven(ctx.F16[1], value);
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}
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Id EmitFPRoundEven32(EmitContext& ctx, Id value) {
return ctx.OpRoundEven(ctx.F32[1], value);
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}
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Id EmitFPRoundEven64(EmitContext& ctx, Id value) {
return ctx.OpRoundEven(ctx.F64[1], value);
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}
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Id EmitFPFloor16(EmitContext& ctx, Id value) {
return ctx.OpFloor(ctx.F16[1], value);
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}
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Id EmitFPFloor32(EmitContext& ctx, Id value) {
return ctx.OpFloor(ctx.F32[1], value);
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}
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Id EmitFPFloor64(EmitContext& ctx, Id value) {
return ctx.OpFloor(ctx.F64[1], value);
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}
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Id EmitFPCeil16(EmitContext& ctx, Id value) {
return ctx.OpCeil(ctx.F16[1], value);
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}
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Id EmitFPCeil32(EmitContext& ctx, Id value) {
return ctx.OpCeil(ctx.F32[1], value);
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}
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Id EmitFPCeil64(EmitContext& ctx, Id value) {
return ctx.OpCeil(ctx.F64[1], value);
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}
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Id EmitFPTrunc16(EmitContext& ctx, Id value) {
return ctx.OpTrunc(ctx.F16[1], value);
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}
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Id EmitFPTrunc32(EmitContext& ctx, Id value) {
return ctx.OpTrunc(ctx.F32[1], value);
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}
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Id EmitFPTrunc64(EmitContext& ctx, Id value) {
return ctx.OpTrunc(ctx.F64[1], value);
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}
} // namespace Shader::Backend::SPIRV