2014-04-09 01:19:26 +02:00
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// Copyright 2014 Citra Emulator Project
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2014-12-17 06:38:14 +01:00
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// Licensed under GPLv2 or any later version
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2014-11-19 09:49:13 +01:00
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// Refer to the license.txt file included.
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2014-04-05 04:26:06 +02:00
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#pragma once
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2018-01-09 22:33:46 +01:00
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#include <array>
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2014-04-09 02:15:08 +02:00
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#include "common/common_types.h"
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2017-10-10 05:56:20 +02:00
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#include "core/hle/kernel/vm_manager.h"
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2014-04-05 04:26:06 +02:00
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2018-08-25 03:43:32 +02:00
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namespace Core {
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2014-04-05 04:26:06 +02:00
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/// Generic ARM11 CPU interface
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2014-04-28 00:29:51 +02:00
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class ARM_Interface : NonCopyable {
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2014-04-05 04:26:06 +02:00
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public:
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virtual ~ARM_Interface() {}
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2014-04-05 04:26:06 +02:00
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2016-12-22 06:08:09 +01:00
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struct ThreadContext {
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2018-01-09 22:33:46 +01:00
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std::array<u64, 31> cpu_registers;
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u64 sp;
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u64 pc;
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u64 cpsr;
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std::array<u128, 32> fpu_registers;
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u64 fpscr;
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};
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2018-02-14 18:47:48 +01:00
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/// Runs the CPU until an event happens
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virtual void Run() = 0;
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2014-05-17 17:59:18 +02:00
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2014-04-05 21:23:59 +02:00
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/// Step CPU by one instruction
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2018-02-14 18:47:48 +01:00
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virtual void Step() = 0;
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2014-05-17 17:59:18 +02:00
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2018-03-16 23:22:14 +01:00
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/// Maps a backing memory region for the CPU
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2018-01-16 19:05:21 +01:00
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virtual void MapBackingMemory(VAddr address, size_t size, u8* memory,
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2018-03-16 23:22:14 +01:00
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Kernel::VMAPermission perms) = 0;
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/// Unmaps a region of memory that was previously mapped using MapBackingMemory
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virtual void UnmapMemory(VAddr address, size_t size) = 0;
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2017-10-10 05:56:20 +02:00
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2016-06-27 20:38:49 +02:00
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/// Clear all instruction cache
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virtual void ClearInstructionCache() = 0;
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2017-09-24 23:44:13 +02:00
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/// Notify CPU emulation that page tables have changed
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virtual void PageTableChanged() = 0;
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2014-04-05 21:23:59 +02:00
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/**
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* Set the Program Counter to an address
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* @param addr Address to set PC to
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*/
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virtual void SetPC(u64 addr) = 0;
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/*
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* Get the current Program Counter
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* @return Returns current PC
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*/
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virtual u64 GetPC() const = 0;
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/**
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* Get an ARM register
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* @param index Register index
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* @return Returns the value in the register
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*/
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virtual u64 GetReg(int index) const = 0;
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2014-04-05 21:23:59 +02:00
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2014-04-11 01:57:56 +02:00
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/**
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* Set an ARM register
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* @param index Register index
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2014-04-11 01:57:56 +02:00
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* @param value Value to set register to
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*/
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virtual void SetReg(int index, u64 value) = 0;
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2018-01-09 22:33:46 +01:00
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virtual u128 GetExtReg(int index) const = 0;
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2018-01-09 22:33:46 +01:00
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virtual void SetExtReg(int index, u128 value) = 0;
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2014-04-11 01:57:56 +02:00
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2015-08-07 03:24:25 +02:00
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/**
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* Gets the value of a VFP register
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* @param index Register index (0-31)
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* @return Returns the value in the register
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*/
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virtual u32 GetVFPReg(int index) const = 0;
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/**
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* Sets a VFP register to the given value
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* @param index Register index (0-31)
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* @param value Value to set register to
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*/
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virtual void SetVFPReg(int index, u32 value) = 0;
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2014-04-05 21:23:59 +02:00
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/**
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* Get the current CPSR register
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* @return Returns the value of the CPSR register
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*/
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2014-11-19 09:49:13 +01:00
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virtual u32 GetCPSR() const = 0;
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2014-04-05 07:23:28 +02:00
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2014-05-12 04:14:13 +02:00
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/**
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* Set the current CPSR register
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* @param cpsr Value to set CPSR to
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*/
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virtual void SetCPSR(u32 cpsr) = 0;
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2017-09-30 20:16:39 +02:00
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virtual VAddr GetTlsAddress() const = 0;
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virtual void SetTlsAddress(VAddr address) = 0;
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2018-07-21 02:57:45 +02:00
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virtual u64 GetTPIDR_EL0() const = 0;
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virtual void SetTPIDR_EL0(u64 value) = 0;
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2014-05-21 00:50:16 +02:00
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/**
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* Saves the current CPU context
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* @param ctx Thread context to save
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*/
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2016-12-22 06:08:09 +01:00
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virtual void SaveContext(ThreadContext& ctx) = 0;
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2014-05-21 00:50:16 +02:00
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/**
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* Loads a CPU context
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* @param ctx Thread context to load
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*/
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2016-12-22 06:08:09 +01:00
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virtual void LoadContext(const ThreadContext& ctx) = 0;
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2014-05-21 00:50:16 +02:00
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2018-07-16 12:24:00 +02:00
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virtual void ClearExclusiveState() = 0;
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2014-06-02 03:40:10 +02:00
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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virtual void PrepareReschedule() = 0;
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2014-04-05 04:26:06 +02:00
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};
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2018-08-25 03:43:32 +02:00
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} // namespace Core
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