2024-03-06 06:26:38 +01:00
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// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
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2022-04-23 10:59:50 +02:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2020-10-27 04:07:36 +01:00
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#pragma once
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2024-03-08 23:44:03 +01:00
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#include <condition_variable>
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#include <deque>
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2020-10-27 04:07:36 +01:00
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#include <memory>
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2024-03-08 23:44:03 +01:00
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#include <mutex>
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#include <thread>
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2020-10-27 04:07:36 +01:00
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#include <vector>
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#include "common/bit_field.h"
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2022-03-19 05:23:48 +01:00
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/polyfill_thread.h"
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#include "core/memory.h"
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2020-10-27 04:07:36 +01:00
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namespace Tegra {
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2022-01-30 10:31:13 +01:00
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namespace Host1x {
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class Control;
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2022-01-30 22:26:01 +01:00
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class Host1x;
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class Nvdec;
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2021-10-01 06:57:02 +02:00
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class SyncptIncrManager;
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class Vic;
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} // namespace Host1x
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enum class ChSubmissionMode : u32 {
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SetClass = 0,
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Incrementing = 1,
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NonIncrementing = 2,
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Mask = 3,
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Immediate = 4,
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Restart = 5,
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Gather = 6,
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};
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enum class ChClassId : u32 {
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NoClass = 0x0,
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Control = 0x1,
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VideoEncodeMpeg = 0x20,
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VideoEncodeNvEnc = 0x21,
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VideoStreamingVi = 0x30,
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VideoStreamingIsp = 0x32,
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VideoStreamingIspB = 0x34,
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VideoStreamingViI2c = 0x36,
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GraphicsVic = 0x5d,
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Graphics3D = 0x60,
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GraphicsGpu = 0x61,
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Tsec = 0xe0,
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TsecB = 0xe1,
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NvJpg = 0xc0,
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NvDec = 0xf0
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};
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union ChCommandHeader {
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u32 raw;
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BitField<0, 16, u32> value;
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BitField<16, 12, u32> method_offset;
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BitField<28, 4, ChSubmissionMode> submission_mode;
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};
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static_assert(sizeof(ChCommandHeader) == sizeof(u32), "ChCommand header is an invalid size");
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struct ChCommand {
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ChClassId class_id{};
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int method_offset{};
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std::vector<u32> arguments;
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};
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2024-03-08 23:44:03 +01:00
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using ChCommandHeaderList =
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Core::Memory::CpuGuestMemory<Tegra::ChCommandHeader, Core::Memory::GuestMemoryFlags::SafeRead>;
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struct ThiRegisters {
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static constexpr std::size_t NUM_REGS = 0x20;
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union {
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struct {
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u32_le increment_syncpt;
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INSERT_PADDING_WORDS_NOINIT(1);
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u32_le increment_syncpt_error;
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u32_le ctx_switch_incremement_syncpt;
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INSERT_PADDING_WORDS_NOINIT(4);
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u32_le ctx_switch;
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INSERT_PADDING_WORDS_NOINIT(1);
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u32_le ctx_syncpt_eof;
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INSERT_PADDING_WORDS_NOINIT(5);
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u32_le method_0;
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u32_le method_1;
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INSERT_PADDING_WORDS_NOINIT(12);
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u32_le int_status;
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u32_le int_mask;
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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};
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enum class ThiMethod : u32 {
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IncSyncpt = offsetof(ThiRegisters, increment_syncpt) / sizeof(u32),
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SetMethod0 = offsetof(ThiRegisters, method_0) / sizeof(u32),
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SetMethod1 = offsetof(ThiRegisters, method_1) / sizeof(u32),
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};
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class CDmaPusher {
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public:
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CDmaPusher() = delete;
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virtual ~CDmaPusher();
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void PushEntries(ChCommandHeaderList&& entries) {
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std::scoped_lock l{command_mutex};
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command_lists.push_back(std::move(entries));
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command_cv.notify_one();
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}
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protected:
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explicit CDmaPusher(Host1x::Host1x& host1x, s32 id);
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virtual void ProcessMethod(u32 method, u32 arg) = 0;
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Host1x::Host1x& host1x;
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Tegra::MemoryManager& memory_manager;
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2020-11-23 19:25:01 +01:00
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private:
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/// Process the command entry
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void ProcessEntries(std::stop_token stop_token);
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/// Invoke command class devices to execute the command based on the current state
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2020-12-04 20:39:12 +01:00
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void ExecuteCommand(u32 state_offset, u32 data);
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std::unique_ptr<Host1x::Control> host_processor;
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std::mutex command_mutex;
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std::condition_variable_any command_cv;
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std::deque<ChCommandHeaderList> command_lists;
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std::jthread thread;
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ThiRegisters thi_regs{};
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ChClassId current_class;
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};
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} // namespace Tegra
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