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Merge pull request #3239 from ReinUsesLisp/p2r
shader/p2r: Implement P2R Pr
This commit is contained in:
commit
028b2718ed
2 changed files with 47 additions and 17 deletions
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@ -1051,7 +1051,7 @@ union Instruction {
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BitField<40, 1, R2pMode> mode;
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BitField<41, 2, u64> byte;
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BitField<20, 7, u64> immediate_mask;
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} r2p;
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} p2r_r2p;
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union {
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BitField<39, 3, u64> pred39;
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@ -1801,6 +1801,7 @@ public:
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PSET,
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CSETP,
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R2P_IMM,
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P2R_IMM,
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XMAD_IMM,
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XMAD_CR,
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XMAD_RC,
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@ -2106,6 +2107,7 @@ private:
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INST("0101000010010---", Id::PSETP, Type::PredicateSetPredicate, "PSETP"),
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INST("010100001010----", Id::CSETP, Type::PredicateSetPredicate, "CSETP"),
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INST("0011100-11110---", Id::R2P_IMM, Type::RegisterSetPredicate, "R2P_IMM"),
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INST("0011100-11101---", Id::P2R_IMM, Type::RegisterSetPredicate, "P2R_IMM"),
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INST("0011011-00------", Id::XMAD_IMM, Type::Xmad, "XMAD_IMM"),
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INST("0100111---------", Id::XMAD_CR, Type::Xmad, "XMAD_CR"),
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INST("010100010-------", Id::XMAD_RC, Type::Xmad, "XMAD_RC"),
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@ -13,37 +13,65 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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namespace {
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constexpr u64 NUM_PROGRAMMABLE_PREDICATES = 7;
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}
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u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED_IF(instr.r2p.mode != Tegra::Shader::R2pMode::Pr);
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UNIMPLEMENTED_IF(instr.p2r_r2p.mode != Tegra::Shader::R2pMode::Pr);
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const Node apply_mask = [&]() {
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const Node apply_mask = [&] {
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM:
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return Immediate(static_cast<u32>(instr.r2p.immediate_mask));
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case OpCode::Id::P2R_IMM:
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return Immediate(static_cast<u32>(instr.p2r_r2p.immediate_mask));
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default:
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UNREACHABLE();
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return Immediate(static_cast<u32>(instr.r2p.immediate_mask));
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return Immediate(0);
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}
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}();
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const Node mask = GetRegister(instr.gpr8);
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const auto offset = static_cast<u32>(instr.r2p.byte) * 8;
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constexpr u32 programmable_preds = 7;
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for (u64 pred = 0; pred < programmable_preds; ++pred) {
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const auto shift = static_cast<u32>(pred);
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const auto offset = static_cast<u32>(instr.p2r_r2p.byte) * 8;
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const Node apply_compare = BitfieldExtract(apply_mask, shift, 1);
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const Node condition =
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Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0));
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM: {
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const Node mask = GetRegister(instr.gpr8);
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const Node value_compare = BitfieldExtract(mask, offset + shift, 1);
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const Node value = Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0));
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for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
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const auto shift = static_cast<u32>(pred);
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const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
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bb.push_back(Conditional(condition, {code}));
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const Node apply_compare = BitfieldExtract(apply_mask, shift, 1);
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const Node condition =
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Operation(OperationCode::LogicalUNotEqual, apply_compare, Immediate(0));
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const Node value_compare = BitfieldExtract(mask, offset + shift, 1);
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const Node value =
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Operation(OperationCode::LogicalUNotEqual, value_compare, Immediate(0));
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const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
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bb.push_back(Conditional(condition, {code}));
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}
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break;
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}
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case OpCode::Id::P2R_IMM: {
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Node value = Immediate(0);
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for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) {
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Node bit = Operation(OperationCode::Select, GetPredicate(pred), Immediate(1U << pred),
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Immediate(0));
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value = Operation(OperationCode::UBitwiseOr, std::move(value), std::move(bit));
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}
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value = Operation(OperationCode::UBitwiseAnd, std::move(value), apply_mask);
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value = BitfieldInsert(GetRegister(instr.gpr8), std::move(value), offset, 8);
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SetRegister(bb, instr.gpr0, std::move(value));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled P2R/R2R instruction: {}", opcode->get().GetName());
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break;
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}
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return pc;
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