N-archive/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-30 10:42:47 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge pull request #292 from lioncash/backports

Browse source 
Backport more skyeye fixes from 3dmoo
This commit is contained in:
bunnei 2014-12-17 20:58:00 -05:00
commit 075126247f
1 changed files with 30 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

49
src/core/arm/interpreter/armemu.cpp
View file

@ -3103,12 +3103,18 @@ mainswitch:
state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000); state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000);
break; break;
} else if ((instr & 0x70) == 0x50) { //pkhtb } else if ((instr & 0x70) == 0x50) { //pkhtb
u8 idest = BITS(12, 15); const u8 rd_idx = BITS(12, 15);
u8 rfis = BITS(16, 19); const u8 rn_idx = BITS(16, 19);
u8 rlast = BITS(0, 3); const u8 rm_idx = BITS(0, 3);
u8 ishi = BITS(7, 11); const u8 imm5 = BITS(7, 11);
if (ishi == 0)ishi = 0x20;
state->Reg[idest] = (((int)(state->Reg[rlast]) >> (int)(ishi))& 0xFFFF) | ((state->Reg[rfis]) & 0xFFFF0000); ARMword val;
if (imm5 >= 32)
val = (state->Reg[rm_idx] >> 31);
else
val = (state->Reg[rm_idx] >> imm5);
state->Reg[rd_idx] = (val & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000);
break; break;
} else if (BIT (4)) { } else if (BIT (4)) {
#ifdef MODE32 #ifdef MODE32
@ -6049,7 +6055,7 @@ L_stm_s_takeabort:
break; break;
} }
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF); Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF;
if (Rm & 0x80) if (Rm & 0x80)
Rm |= 0xffffff00; Rm |= 0xffffff00;
@ -6058,11 +6064,12 @@ L_stm_s_takeabort:
state->Reg[BITS(12, 15)] = Rm; state->Reg[BITS(12, 15)] = Rm;
else else
/* SXTAB */ /* SXTAB */
state->Reg[BITS(12, 15)] += Rm; state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
return 1; return 1;
} }
case 0x6b: { case 0x6b:
{
ARMword Rm; ARMword Rm;
int ror = -1; int ror = -1;
@ -6080,10 +6087,10 @@ L_stm_s_takeabort:
ror = 24; ror = 24;
break; break;
case 0xf3: case 0xf3: // REV
DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24); DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24);
return 1; return 1;
case 0xfb: case 0xfb: // REV16
DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8); DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8);
return 1; return 1;
default: default:
@ -6093,7 +6100,7 @@ L_stm_s_takeabort:
if (ror == -1) if (ror == -1)
break; break;
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF); Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF;
if (Rm & 0x8000) if (Rm & 0x8000)
Rm |= 0xffff0000; Rm |= 0xffff0000;
@ -6180,7 +6187,7 @@ L_stm_s_takeabort:
break; break;
} }
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF); Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF;
if (BITS(16, 19) == 0xf) if (BITS(16, 19) == 0xf)
/* UXTB */ /* UXTB */
@ -6210,9 +6217,13 @@ L_stm_s_takeabort:
ror = 24; ror = 24;
break; break;
case 0xfb: case 0xfb: // REVSH
printf("Unhandled v6 insn: revsh\n"); {
return 0; DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8);
if (DEST & 0x8000)
DEST |= 0xffff0000;
return 1;
}
default: default:
break; break;
} }
@ -6220,13 +6231,13 @@ L_stm_s_takeabort:
if (ror == -1) if (ror == -1)
break; break;
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF); Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF;
/* UXT */ /* UXT */
/* state->Reg[BITS (12, 15)] = Rm; */ /* state->Reg[BITS (12, 15)] = Rm; */
/* dyf add */ /* dyf add */
if (BITS(16, 19) == 0xf) { if (BITS(16, 19) == 0xf) {
state->Reg[BITS(12, 15)] = (Rm >> (8 * BITS(10, 11))) & 0x0000FFFF; state->Reg[BITS(12, 15)] = Rm;
} }
else { else {
/* UXTAH */ /* UXTAH */
@ -6234,7 +6245,7 @@ L_stm_s_takeabort:
// printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)] // printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
// , Rm, BITS(10, 11)); // , Rm, BITS(10, 11));
// printf("icounter is %lld\n", state->NumInstrs); // printf("icounter is %lld\n", state->NumInstrs);
state->Reg[BITS(12, 15)] = (state->Reg[BITS(16, 19)] >> (8 * (BITS(10, 11)))) + Rm; state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
// printf("rd is %x\n", state->Reg[BITS (12, 15)]); // printf("rd is %x\n", state->Reg[BITS (12, 15)]);
// exit(-1); // exit(-1);
} }