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Merge pull request #4100 from MerryMage/no-a32-interp
arm_dynarmic: CP15 changes
This commit is contained in:
Fernando Sahmkow
GitHub
commit
1394a581f2
4 changed files with 89 additions and 144 deletions
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@ -50,7 +50,8 @@ public:
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}
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void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
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UNIMPLEMENTED();
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UNIMPLEMENTED_MSG("This should never happen, pc = {:08X}, code = {:08X}", pc,
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MemoryReadCode(pc));
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}
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void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override {
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@ -89,8 +90,6 @@ public:
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ARM_Dynarmic_32& parent;
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std::size_t num_interpreted_instructions{};
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u64 tpidrro_el0{};
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u64 tpidr_el0{};
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};
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std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable& page_table,
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@ -99,7 +98,7 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable&
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config.callbacks = cb.get();
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// TODO(bunnei): Implement page table for 32-bit
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// config.page_table = &page_table.pointers;
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config.coprocessors[15] = std::make_shared<DynarmicCP15>((u32*)&CP15_regs[0]);
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config.coprocessors[15] = cp15;
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config.define_unpredictable_behaviour = true;
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return std::make_unique<Dynarmic::A32::Jit>(config);
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}
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@ -112,13 +111,13 @@ void ARM_Dynarmic_32::Run() {
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}
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void ARM_Dynarmic_32::Step() {
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cb->InterpreterFallback(jit->Regs()[15], 1);
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jit->Step();
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}
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ARM_Dynarmic_32::ARM_Dynarmic_32(System& system, ExclusiveMonitor& exclusive_monitor,
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std::size_t core_index)
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: ARM_Interface{system},
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cb(std::make_unique<DynarmicCallbacks32>(*this)), core_index{core_index},
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: ARM_Interface{system}, cb(std::make_unique<DynarmicCallbacks32>(*this)),
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cp15(std::make_shared<DynarmicCP15>(*this)), core_index{core_index},
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exclusive_monitor{dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor)} {}
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ARM_Dynarmic_32::~ARM_Dynarmic_32() = default;
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@ -154,19 +153,19 @@ void ARM_Dynarmic_32::SetPSTATE(u32 cpsr) {
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}
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u64 ARM_Dynarmic_32::GetTlsAddress() const {
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return CP15_regs[static_cast<std::size_t>(CP15Register::CP15_THREAD_URO)];
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return cp15->uro;
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}
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void ARM_Dynarmic_32::SetTlsAddress(VAddr address) {
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CP15_regs[static_cast<std::size_t>(CP15Register::CP15_THREAD_URO)] = static_cast<u32>(address);
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cp15->uro = static_cast<u32>(address);
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}
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u64 ARM_Dynarmic_32::GetTPIDR_EL0() const {
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return cb->tpidr_el0;
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return cp15->uprw;
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}
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void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
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cb->tpidr_el0 = value;
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cp15->uprw = value;
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}
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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@ -22,6 +22,7 @@ class Memory;
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namespace Core {
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class DynarmicCallbacks32;
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class DynarmicCP15;
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class DynarmicExclusiveMonitor;
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class System;
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@ -66,12 +67,14 @@ private:
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std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A32::Jit>, Common::PairHash>;
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friend class DynarmicCallbacks32;
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friend class DynarmicCP15;
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std::unique_ptr<DynarmicCallbacks32> cb;
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JitCacheType jit_cache;
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std::shared_ptr<Dynarmic::A32::Jit> jit;
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std::shared_ptr<DynarmicCP15> cp15;
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std::size_t core_index;
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DynarmicExclusiveMonitor& exclusive_monitor;
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std::array<u32, 84> CP15_regs{};
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};
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} // namespace Core
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@ -2,79 +2,132 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <fmt/format.h>
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#include "common/logging/log.h"
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#include "core/arm/dynarmic/arm_dynarmic_32.h"
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/core_timing_util.h"
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using Callback = Dynarmic::A32::Coprocessor::Callback;
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using CallbackOrAccessOneWord = Dynarmic::A32::Coprocessor::CallbackOrAccessOneWord;
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using CallbackOrAccessTwoWords = Dynarmic::A32::Coprocessor::CallbackOrAccessTwoWords;
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template <>
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struct fmt::formatter<Dynarmic::A32::CoprocReg> {
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constexpr auto parse(format_parse_context& ctx) {
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return ctx.begin();
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}
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template <typename FormatContext>
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auto format(const Dynarmic::A32::CoprocReg& reg, FormatContext& ctx) {
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return format_to(ctx.out(), "cp{}", static_cast<size_t>(reg));
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}
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};
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namespace Core {
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static u32 dummy_value;
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std::optional<Callback> DynarmicCP15::CompileInternalOperation(bool two, unsigned opc1,
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CoprocReg CRd, CoprocReg CRn,
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CoprocReg CRm, unsigned opc2) {
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LOG_CRITICAL(Core_ARM, "CP15: cdp{} p15, {}, {}, {}, {}, {}", two ? "2" : "", opc1, CRd, CRn,
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CRm, opc2);
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return {};
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}
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CallbackOrAccessOneWord DynarmicCP15::CompileSendOneWord(bool two, unsigned opc1, CoprocReg CRn,
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CoprocReg CRm, unsigned opc2) {
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// TODO(merry): Privileged CP15 registers
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if (!two && CRn == CoprocReg::C7 && opc1 == 0 && CRm == CoprocReg::C5 && opc2 == 4) {
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// CP15_FLUSH_PREFETCH_BUFFER
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// This is a dummy write, we ignore the value written here.
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_FLUSH_PREFETCH_BUFFER)];
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return &dummy_value;
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}
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if (!two && CRn == CoprocReg::C7 && opc1 == 0 && CRm == CoprocReg::C10) {
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switch (opc2) {
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case 4:
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// CP15_DATA_SYNC_BARRIER
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// This is a dummy write, we ignore the value written here.
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_DATA_SYNC_BARRIER)];
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return &dummy_value;
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case 5:
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// CP15_DATA_MEMORY_BARRIER
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// This is a dummy write, we ignore the value written here.
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_DATA_MEMORY_BARRIER)];
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default:
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return {};
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return &dummy_value;
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}
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}
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if (!two && CRn == CoprocReg::C13 && opc1 == 0 && CRm == CoprocReg::C0 && opc2 == 2) {
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_THREAD_UPRW)];
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// CP15_THREAD_UPRW
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return &uprw;
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}
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LOG_CRITICAL(Core_ARM, "CP15: mcr{} p15, {}, <Rt>, {}, {}, {}", two ? "2" : "", opc1, CRn, CRm,
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opc2);
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return {};
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}
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CallbackOrAccessTwoWords DynarmicCP15::CompileSendTwoWords(bool two, unsigned opc, CoprocReg CRm) {
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LOG_CRITICAL(Core_ARM, "CP15: mcrr{} p15, {}, <Rt>, <Rt2>, {}", two ? "2" : "", opc, CRm);
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return {};
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}
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CallbackOrAccessOneWord DynarmicCP15::CompileGetOneWord(bool two, unsigned opc1, CoprocReg CRn,
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CoprocReg CRm, unsigned opc2) {
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// TODO(merry): Privileged CP15 registers
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if (!two && CRn == CoprocReg::C13 && opc1 == 0 && CRm == CoprocReg::C0) {
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switch (opc2) {
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case 2:
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_THREAD_UPRW)];
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// CP15_THREAD_UPRW
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return &uprw;
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case 3:
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_THREAD_URO)];
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default:
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return {};
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// CP15_THREAD_URO
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return &uro;
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}
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}
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LOG_CRITICAL(Core_ARM, "CP15: mrc{} p15, {}, <Rt>, {}, {}, {}", two ? "2" : "", opc1, CRn, CRm,
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opc2);
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return {};
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}
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CallbackOrAccessTwoWords DynarmicCP15::CompileGetTwoWords(bool two, unsigned opc, CoprocReg CRm) {
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if (!two && opc == 0 && CRm == CoprocReg::C14) {
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// CNTPCT
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const auto callback = static_cast<u64 (*)(Dynarmic::A32::Jit*, void*, u32, u32)>(
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[](Dynarmic::A32::Jit*, void* arg, u32, u32) -> u64 {
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ARM_Dynarmic_32& parent = *(ARM_Dynarmic_32*)arg;
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return Timing::CpuCyclesToClockCycles(parent.system.CoreTiming().GetTicks());
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});
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return Dynarmic::A32::Coprocessor::Callback{callback, (void*)&parent};
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}
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LOG_CRITICAL(Core_ARM, "CP15: mrrc{} p15, {}, <Rt>, <Rt2>, {}", two ? "2" : "", opc, CRm);
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return {};
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}
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std::optional<Callback> DynarmicCP15::CompileLoadWords(bool two, bool long_transfer, CoprocReg CRd,
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std::optional<u8> option) {
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if (option) {
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LOG_CRITICAL(Core_ARM, "CP15: mrrc{}{} p15, {}, [...], {}", two ? "2" : "",
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long_transfer ? "l" : "", CRd, *option);
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} else {
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LOG_CRITICAL(Core_ARM, "CP15: mrrc{}{} p15, {}, [...]", two ? "2" : "",
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long_transfer ? "l" : "", CRd);
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}
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return {};
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}
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std::optional<Callback> DynarmicCP15::CompileStoreWords(bool two, bool long_transfer, CoprocReg CRd,
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std::optional<u8> option) {
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if (option) {
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LOG_CRITICAL(Core_ARM, "CP15: mrrc{}{} p15, {}, [...], {}", two ? "2" : "",
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long_transfer ? "l" : "", CRd, *option);
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} else {
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LOG_CRITICAL(Core_ARM, "CP15: mrrc{}{} p15, {}, [...]", two ? "2" : "",
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long_transfer ? "l" : "", CRd);
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}
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return {};
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}
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} // namespace Core
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@ -10,128 +10,15 @@
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#include <dynarmic/A32/coprocessor.h>
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#include "common/common_types.h"
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enum class CP15Register {
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// c0 - Information registers
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CP15_MAIN_ID,
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CP15_CACHE_TYPE,
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CP15_TCM_STATUS,
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CP15_TLB_TYPE,
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CP15_CPU_ID,
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CP15_PROCESSOR_FEATURE_0,
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CP15_PROCESSOR_FEATURE_1,
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CP15_DEBUG_FEATURE_0,
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CP15_AUXILIARY_FEATURE_0,
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CP15_MEMORY_MODEL_FEATURE_0,
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CP15_MEMORY_MODEL_FEATURE_1,
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CP15_MEMORY_MODEL_FEATURE_2,
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CP15_MEMORY_MODEL_FEATURE_3,
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CP15_ISA_FEATURE_0,
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CP15_ISA_FEATURE_1,
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CP15_ISA_FEATURE_2,
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CP15_ISA_FEATURE_3,
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CP15_ISA_FEATURE_4,
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namespace Core {
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// c1 - Control registers
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CP15_CONTROL,
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CP15_AUXILIARY_CONTROL,
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CP15_COPROCESSOR_ACCESS_CONTROL,
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// c2 - Translation table registers
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CP15_TRANSLATION_BASE_TABLE_0,
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CP15_TRANSLATION_BASE_TABLE_1,
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CP15_TRANSLATION_BASE_CONTROL,
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CP15_DOMAIN_ACCESS_CONTROL,
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CP15_RESERVED,
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// c5 - Fault status registers
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CP15_FAULT_STATUS,
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CP15_INSTR_FAULT_STATUS,
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CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
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CP15_INST_FSR,
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// c6 - Fault Address registers
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CP15_FAULT_ADDRESS,
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CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
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CP15_WFAR,
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CP15_IFAR,
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// c7 - Cache operation registers
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CP15_WAIT_FOR_INTERRUPT,
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CP15_PHYS_ADDRESS,
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CP15_INVALIDATE_INSTR_CACHE,
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CP15_INVALIDATE_INSTR_CACHE_USING_MVA,
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CP15_INVALIDATE_INSTR_CACHE_USING_INDEX,
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CP15_FLUSH_PREFETCH_BUFFER,
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CP15_FLUSH_BRANCH_TARGET_CACHE,
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CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY,
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CP15_INVALIDATE_DATA_CACHE,
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CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA,
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CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX,
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CP15_INVALIDATE_DATA_AND_INSTR_CACHE,
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CP15_CLEAN_DATA_CACHE,
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CP15_CLEAN_DATA_CACHE_LINE_USING_MVA,
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CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX,
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CP15_DATA_SYNC_BARRIER,
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CP15_DATA_MEMORY_BARRIER,
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CP15_CLEAN_AND_INVALIDATE_DATA_CACHE,
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CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA,
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CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX,
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// c8 - TLB operations
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CP15_INVALIDATE_ITLB,
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CP15_INVALIDATE_ITLB_SINGLE_ENTRY,
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CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH,
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CP15_INVALIDATE_ITLB_ENTRY_ON_MVA,
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CP15_INVALIDATE_DTLB,
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CP15_INVALIDATE_DTLB_SINGLE_ENTRY,
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CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH,
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CP15_INVALIDATE_DTLB_ENTRY_ON_MVA,
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CP15_INVALIDATE_UTLB,
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CP15_INVALIDATE_UTLB_SINGLE_ENTRY,
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CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH,
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CP15_INVALIDATE_UTLB_ENTRY_ON_MVA,
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// c9 - Data cache lockdown register
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CP15_DATA_CACHE_LOCKDOWN,
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// c10 - TLB/Memory map registers
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CP15_TLB_LOCKDOWN,
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CP15_PRIMARY_REGION_REMAP,
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CP15_NORMAL_REGION_REMAP,
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// c13 - Thread related registers
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CP15_PID,
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CP15_CONTEXT_ID,
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CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write
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CP15_THREAD_URO, // Thread ID register - User Read Only (Privileged R/W)
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CP15_THREAD_PRW, // Thread ID register - Privileged R/W only.
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// c15 - Performance and TLB lockdown registers
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CP15_PERFORMANCE_MONITOR_CONTROL,
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CP15_CYCLE_COUNTER,
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CP15_COUNT_0,
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CP15_COUNT_1,
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CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY,
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CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY,
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CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS,
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CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS,
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CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE,
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CP15_TLB_DEBUG_CONTROL,
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// Skyeye defined
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CP15_TLB_FAULT_ADDR,
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CP15_TLB_FAULT_STATUS,
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// Not an actual register.
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// All registers should be defined above this.
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CP15_REGISTER_COUNT,
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};
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class ARM_Dynarmic_32;
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class DynarmicCP15 final : public Dynarmic::A32::Coprocessor {
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public:
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using CoprocReg = Dynarmic::A32::CoprocReg;
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explicit DynarmicCP15(u32* cp15) : CP15(cp15){};
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explicit DynarmicCP15(ARM_Dynarmic_32& parent) : parent(parent) {}
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std::optional<Callback> CompileInternalOperation(bool two, unsigned opc1, CoprocReg CRd,
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CoprocReg CRn, CoprocReg CRm,
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@ -147,6 +34,9 @@ public:
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std::optional<Callback> CompileStoreWords(bool two, bool long_transfer, CoprocReg CRd,
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std::optional<u8> option) override;
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private:
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u32* CP15{};
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ARM_Dynarmic_32& parent;
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u32 uprw;
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u32 uro;
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};
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} // namespace Core
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