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maxwell_dma: Rename registers to match official docs and reorder
Rename registers in the MaxwellDMA class to match Nvidia's official documentation. This one can be found here: https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/dma-copy/clb0b5.h While we are at it, reorganize the code in MaxwellDMA to be separated in different functions.
This commit is contained in:
ReinUsesLisp
parent
6ae0b83442
commit
2a9d17b7e7
2 changed files with 379 additions and 311 deletions
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@ -14,50 +14,44 @@
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namespace Tegra::Engines {
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using namespace Texture;
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MaxwellDMA::MaxwellDMA(Core::System& system, MemoryManager& memory_manager)
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: system{system}, memory_manager{memory_manager} {}
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void MaxwellDMA::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid MaxwellDMA register, increase the size of the Regs structure");
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ASSERT_MSG(method < NUM_REGS, "Invalid MaxwellDMA register");
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regs.reg_array[method] = method_argument;
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#define MAXWELLDMA_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::MaxwellDMA::Regs, field_name) / sizeof(u32))
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switch (method) {
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case MAXWELLDMA_REG_INDEX(exec): {
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HandleCopy();
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break;
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if (method == offsetof(Regs, launch_dma) / sizeof(u32)) {
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Launch();
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}
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}
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#undef MAXWELLDMA_REG_INDEX
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}
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void MaxwellDMA::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) {
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for (std::size_t i = 0; i < amount; i++) {
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for (size_t i = 0; i < amount; ++i) {
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CallMethod(method, base_start[i], methods_pending - static_cast<u32>(i) <= 1);
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}
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}
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void MaxwellDMA::HandleCopy() {
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void MaxwellDMA::Launch() {
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LOG_TRACE(HW_GPU, "Requested a DMA copy");
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const GPUVAddr source = regs.src_address.Address();
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const GPUVAddr dest = regs.dst_address.Address();
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// TODO(Subv): Perform more research and implement all features of this engine.
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ASSERT(regs.exec.enable_swizzle == 0);
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ASSERT(regs.exec.query_mode == Regs::QueryMode::None);
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ASSERT(regs.exec.query_intr == Regs::QueryIntr::None);
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ASSERT(regs.exec.copy_mode == Regs::CopyMode::Unk2);
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ASSERT(regs.dst_params.pos_x == 0);
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ASSERT(regs.dst_params.pos_y == 0);
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const LaunchDMA& launch = regs.launch_dma;
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ASSERT(launch.remap_enable == 0);
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ASSERT(launch.semaphore_type == LaunchDMA::SemaphoreType::NONE);
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ASSERT(launch.interrupt_type == LaunchDMA::InterruptType::NONE);
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ASSERT(launch.data_transfer_type == LaunchDMA::DataTransferType::NON_PIPELINED);
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ASSERT(regs.dst_params.origin.x == 0);
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ASSERT(regs.dst_params.origin.y == 0);
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if (!regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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const bool is_src_pitch = launch.src_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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const bool is_dst_pitch = launch.dst_memory_layout == LaunchDMA::MemoryLayout::PITCH;
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if (!is_src_pitch && !is_dst_pitch) {
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// If both the source and the destination are in block layout, assert.
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UNREACHABLE_MSG("Tiled->Tiled DMA transfers are not yet implemented");
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return;
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@ -66,42 +60,133 @@ void MaxwellDMA::HandleCopy() {
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// All copies here update the main memory, so mark all rasterizer states as invalid.
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system.GPU().Maxwell3D().OnMemoryWrite();
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if (regs.exec.is_dst_linear && regs.exec.is_src_linear) {
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// When the enable_2d bit is disabled, the copy is performed as if we were copying a 1D
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// buffer of length `x_count`, otherwise we copy a 2D image of dimensions (x_count,
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// y_count).
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if (!regs.exec.enable_2d) {
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memory_manager.CopyBlock(dest, source, regs.x_count);
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if (is_src_pitch && is_dst_pitch) {
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CopyPitchToPitch();
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} else {
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ASSERT(launch.multi_line_enable == 1);
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if (!is_src_pitch && is_dst_pitch) {
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CopyBlockLinearToPitch();
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} else {
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CopyPitchToBlockLinear();
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}
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}
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}
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void MaxwellDMA::CopyPitchToPitch() {
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// When `multi_line_enable` bit is disabled the copy is performed as if we were copying a 1D
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// buffer of length `line_length_in`.
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// Otherwise we copy a 2D image of dimensions (line_length_in, line_count).
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if (!regs.launch_dma.multi_line_enable) {
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memory_manager.CopyBlock(regs.offset_out, regs.offset_in, regs.line_length_in);
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return;
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}
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// If both the source and the destination are in linear layout, perform a line-by-line
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// copy. We're going to take a subrect of size (x_count, y_count) from the source
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// rectangle. There is no need to manually flush/invalidate the regions because
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// CopyBlock does that for us.
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for (u32 line = 0; line < regs.y_count; ++line) {
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const GPUVAddr source_line = source + line * regs.src_pitch;
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const GPUVAddr dest_line = dest + line * regs.dst_pitch;
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memory_manager.CopyBlock(dest_line, source_line, regs.x_count);
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// Perform a line-by-line copy.
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// We're going to take a subrect of size (line_length_in, line_count) from the source rectangle.
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// There is no need to manually flush/invalidate the regions because CopyBlock does that for us.
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for (u32 line = 0; line < regs.line_count; ++line) {
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const GPUVAddr source_line = regs.offset_in + static_cast<size_t>(line) * regs.pitch_in;
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const GPUVAddr dest_line = regs.offset_out + static_cast<size_t>(line) * regs.pitch_out;
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memory_manager.CopyBlock(dest_line, source_line, regs.line_length_in);
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}
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return;
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}
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ASSERT(regs.exec.enable_2d == 1);
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void MaxwellDMA::CopyBlockLinearToPitch() {
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ASSERT(regs.src_params.block_size.depth == 0);
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if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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ASSERT(regs.src_params.BlockDepth() == 0);
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// Optimized path for micro copies.
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if (regs.dst_pitch * regs.y_count < Texture::GetGOBSize() && regs.dst_pitch <= 64) {
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const u32 bytes_per_pixel = regs.dst_pitch / regs.x_count;
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const std::size_t src_size = Texture::GetGOBSize();
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const std::size_t dst_size = regs.dst_pitch * regs.y_count;
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u32 pos_x = regs.src_params.pos_x;
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u32 pos_y = regs.src_params.pos_y;
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const u64 offset =
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Texture::GetGOBOffset(regs.src_params.size_x, regs.src_params.size_y, pos_x, pos_y,
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regs.src_params.BlockDepth(), bytes_per_pixel);
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const size_t dst_size = static_cast<size_t>(regs.pitch_out) * regs.line_count;
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if (dst_size < GetGOBSize() && regs.pitch_out <= 64) {
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FastCopyBlockLinearToPitch();
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return;
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}
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// Deswizzle the input and copy it over.
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const u32 bytes_per_pixel = regs.pitch_out / regs.line_length_in;
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const Parameters& src_params = regs.src_params;
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const u32 width = src_params.width;
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const u32 height = src_params.height;
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const u32 depth = src_params.depth;
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const u32 block_height = src_params.block_size.height;
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const u32 block_depth = src_params.block_size.depth;
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const size_t src_size =
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CalculateSize(true, bytes_per_pixel, width, height, depth, block_height, block_depth);
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const size_t src_layer_size =
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CalculateSize(true, bytes_per_pixel, width, height, 1, block_height, block_depth);
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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if (Settings::IsGPULevelExtreme()) {
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memory_manager.ReadBlock(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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} else {
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memory_manager.ReadBlockUnsafe(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(regs.offset_out, write_buffer.data(), dst_size);
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}
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UnswizzleSubrect(regs.line_length_in, regs.line_count, regs.pitch_out, src_params.width,
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bytes_per_pixel, read_buffer.data() + src_layer_size * src_params.layer,
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write_buffer.data(), src_params.block_size.height, src_params.origin.x,
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src_params.origin.y);
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::CopyPitchToBlockLinear() {
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const auto& dst_params = regs.dst_params;
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ASSERT(dst_params.block_size.depth == 0);
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const u32 bytes_per_pixel = regs.pitch_in / regs.line_length_in;
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const u32 width = dst_params.width;
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const u32 height = dst_params.height;
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const u32 depth = dst_params.depth;
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const u32 block_height = dst_params.block_size.height;
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const u32 block_depth = dst_params.block_size.depth;
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const size_t dst_size =
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CalculateSize(true, bytes_per_pixel, width, height, depth, block_height, block_depth);
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const size_t dst_layer_size =
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CalculateSize(true, bytes_per_pixel, width, height, 1, block_height, block_depth);
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const size_t src_size = static_cast<size_t>(regs.pitch_in) * regs.line_count;
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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if (Settings::IsGPULevelExtreme()) {
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memory_manager.ReadBlock(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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} else {
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memory_manager.ReadBlockUnsafe(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(regs.offset_out, write_buffer.data(), dst_size);
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}
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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SwizzleSubrect(regs.line_length_in, regs.line_count, regs.pitch_in, dst_params.width,
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bytes_per_pixel, write_buffer.data() + dst_layer_size * dst_params.layer,
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read_buffer.data(), dst_params.block_size.height, dst_params.origin.x,
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dst_params.origin.y);
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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}
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void MaxwellDMA::FastCopyBlockLinearToPitch() {
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const u32 bytes_per_pixel = regs.pitch_out / regs.line_length_in;
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const size_t src_size = GetGOBSize();
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const size_t dst_size = static_cast<size_t>(regs.pitch_out) * regs.line_count;
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u32 pos_x = regs.src_params.origin.x;
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u32 pos_y = regs.src_params.origin.y;
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const u64 offset = GetGOBOffset(regs.src_params.width, regs.src_params.height, pos_x, pos_y,
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regs.src_params.block_size.height, bytes_per_pixel);
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const u32 x_in_gob = 64 / bytes_per_pixel;
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pos_x = pos_x % x_in_gob;
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pos_y = pos_y % 8;
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@ -115,95 +200,18 @@ void MaxwellDMA::HandleCopy() {
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}
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if (Settings::IsGPULevelExtreme()) {
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memory_manager.ReadBlock(source + offset, read_buffer.data(), src_size);
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memory_manager.ReadBlock(dest, write_buffer.data(), dst_size);
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memory_manager.ReadBlock(regs.offset_in + offset, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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} else {
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memory_manager.ReadBlockUnsafe(source + offset, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(dest, write_buffer.data(), dst_size);
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memory_manager.ReadBlockUnsafe(regs.offset_in + offset, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(regs.offset_out, write_buffer.data(), dst_size);
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}
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Texture::UnswizzleSubrect(regs.x_count, regs.y_count, regs.dst_pitch,
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regs.src_params.size_x, bytes_per_pixel, read_buffer.data(),
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write_buffer.data(), regs.src_params.BlockHeight(), pos_x,
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pos_y);
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UnswizzleSubrect(regs.line_length_in, regs.line_count, regs.pitch_out, regs.src_params.width,
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bytes_per_pixel, read_buffer.data(), write_buffer.data(),
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regs.src_params.block_size.height, pos_x, pos_y);
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memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
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return;
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}
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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const u32 bytes_per_pixel = regs.dst_pitch / regs.x_count;
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const std::size_t src_size = Texture::CalculateSize(
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true, bytes_per_pixel, regs.src_params.size_x, regs.src_params.size_y,
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regs.src_params.size_z, regs.src_params.BlockHeight(), regs.src_params.BlockDepth());
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const std::size_t src_layer_size = Texture::CalculateSize(
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true, bytes_per_pixel, regs.src_params.size_x, regs.src_params.size_y, 1,
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regs.src_params.BlockHeight(), regs.src_params.BlockDepth());
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const std::size_t dst_size = regs.dst_pitch * regs.y_count;
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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if (Settings::IsGPULevelExtreme()) {
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memory_manager.ReadBlock(source, read_buffer.data(), src_size);
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memory_manager.ReadBlock(dest, write_buffer.data(), dst_size);
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} else {
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memory_manager.ReadBlockUnsafe(source, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(dest, write_buffer.data(), dst_size);
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}
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Texture::UnswizzleSubrect(
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regs.x_count, regs.y_count, regs.dst_pitch, regs.src_params.size_x, bytes_per_pixel,
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read_buffer.data() + src_layer_size * regs.src_params.pos_z, write_buffer.data(),
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regs.src_params.BlockHeight(), regs.src_params.pos_x, regs.src_params.pos_y);
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memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
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} else {
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ASSERT(regs.dst_params.BlockDepth() == 0);
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const u32 bytes_per_pixel = regs.src_pitch / regs.x_count;
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const std::size_t dst_size = Texture::CalculateSize(
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true, bytes_per_pixel, regs.dst_params.size_x, regs.dst_params.size_y,
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regs.dst_params.size_z, regs.dst_params.BlockHeight(), regs.dst_params.BlockDepth());
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const std::size_t dst_layer_size = Texture::CalculateSize(
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true, bytes_per_pixel, regs.dst_params.size_x, regs.dst_params.size_y, 1,
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regs.dst_params.BlockHeight(), regs.dst_params.BlockDepth());
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const std::size_t src_size = regs.src_pitch * regs.y_count;
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if (read_buffer.size() < src_size) {
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read_buffer.resize(src_size);
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}
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if (write_buffer.size() < dst_size) {
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write_buffer.resize(dst_size);
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}
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if (Settings::IsGPULevelExtreme()) {
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memory_manager.ReadBlock(source, read_buffer.data(), src_size);
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memory_manager.ReadBlock(dest, write_buffer.data(), dst_size);
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} else {
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memory_manager.ReadBlockUnsafe(source, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(dest, write_buffer.data(), dst_size);
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}
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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Texture::SwizzleSubrect(
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regs.x_count, regs.y_count, regs.src_pitch, regs.dst_params.size_x, bytes_per_pixel,
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write_buffer.data() + dst_layer_size * regs.dst_params.pos_z, read_buffer.data(),
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regs.dst_params.BlockHeight(), regs.dst_params.pos_x, regs.dst_params.pos_y);
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memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
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}
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memory_manager.WriteBlock(regs.offset_out, write_buffer.data(), dst_size);
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}
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} // namespace Tegra::Engines
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@ -24,12 +24,167 @@ class MemoryManager;
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namespace Tegra::Engines {
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/**
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* This Engine is known as GK104_Copy. Documentation can be found in:
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* This engine is known as gk104_copy. Documentation can be found in:
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* https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/dma-copy/clb0b5.h
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* https://github.com/envytools/envytools/blob/master/rnndb/fifo/gk104_copy.xml
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*/
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class MaxwellDMA final : public EngineInterface {
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public:
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struct PackedGPUVAddr {
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u32 upper;
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u32 lower;
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constexpr operator GPUVAddr() const noexcept {
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return (static_cast<GPUVAddr>(upper & 0xff) << 32) | lower;
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}
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};
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union BlockSize {
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BitField<0, 4, u32> width;
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BitField<4, 4, u32> height;
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BitField<8, 4, u32> depth;
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BitField<12, 4, u32> gob_height;
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};
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static_assert(sizeof(BlockSize) == 4);
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union Origin {
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BitField<0, 16, u32> x;
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BitField<16, 16, u32> y;
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};
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static_assert(sizeof(Origin) == 4);
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struct Parameters {
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BlockSize block_size;
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u32 width;
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u32 height;
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u32 depth;
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u32 layer;
|
||||
Origin origin;
|
||||
};
|
||||
static_assert(sizeof(Parameters) == 24);
|
||||
|
||||
struct Semaphore {
|
||||
PackedGPUVAddr address;
|
||||
u32 payload;
|
||||
};
|
||||
static_assert(sizeof(Semaphore) == 12);
|
||||
|
||||
struct RenderEnable {
|
||||
enum class Mode : u32 {
|
||||
FALSE = 0,
|
||||
TRUE = 1,
|
||||
CONDITIONAL = 2,
|
||||
RENDER_IF_EQUAL = 3,
|
||||
RENDER_IF_NOT_EQUAL = 4,
|
||||
};
|
||||
|
||||
PackedGPUVAddr address;
|
||||
BitField<0, 3, Mode> mode;
|
||||
};
|
||||
static_assert(sizeof(RenderEnable) == 12);
|
||||
|
||||
enum class PhysModeTarget : u32 {
|
||||
LOCAL_FB = 0,
|
||||
COHERENT_SYSMEM = 1,
|
||||
NONCOHERENT_SYSMEM = 2,
|
||||
};
|
||||
using PhysMode = BitField<0, 2, PhysModeTarget>;
|
||||
|
||||
union LaunchDMA {
|
||||
enum class DataTransferType : u32 {
|
||||
NONE = 0,
|
||||
PIPELINED = 1,
|
||||
NON_PIPELINED = 2,
|
||||
};
|
||||
|
||||
enum class SemaphoreType : u32 {
|
||||
NONE = 0,
|
||||
RELEASE_ONE_WORD_SEMAPHORE = 1,
|
||||
RELEASE_FOUR_WORD_SEMAPHORE = 2,
|
||||
};
|
||||
|
||||
enum class InterruptType : u32 {
|
||||
NONE = 0,
|
||||
BLOCKING = 1,
|
||||
NON_BLOCKING = 2,
|
||||
};
|
||||
|
||||
enum class MemoryLayout : u32 {
|
||||
BLOCKLINEAR = 0,
|
||||
PITCH = 1,
|
||||
};
|
||||
|
||||
enum class Type : u32 {
|
||||
VIRTUAL = 0,
|
||||
PHYSICAL = 1,
|
||||
};
|
||||
|
||||
enum class SemaphoreReduction : u32 {
|
||||
IMIN = 0,
|
||||
IMAX = 1,
|
||||
IXOR = 2,
|
||||
IAND = 3,
|
||||
IOR = 4,
|
||||
IADD = 5,
|
||||
INC = 6,
|
||||
DEC = 7,
|
||||
FADD = 0xA,
|
||||
};
|
||||
|
||||
enum class SemaphoreReductionSign : u32 {
|
||||
SIGNED = 0,
|
||||
UNSIGNED = 1,
|
||||
};
|
||||
|
||||
enum class BypassL2 : u32 {
|
||||
USE_PTE_SETTING = 0,
|
||||
FORCE_VOLATILE = 1,
|
||||
};
|
||||
|
||||
BitField<0, 2, DataTransferType> data_transfer_type;
|
||||
BitField<2, 1, u32> flush_enable;
|
||||
BitField<3, 2, SemaphoreType> semaphore_type;
|
||||
BitField<5, 2, InterruptType> interrupt_type;
|
||||
BitField<7, 1, MemoryLayout> src_memory_layout;
|
||||
BitField<8, 1, MemoryLayout> dst_memory_layout;
|
||||
BitField<9, 1, u32> multi_line_enable;
|
||||
BitField<10, 1, u32> remap_enable;
|
||||
BitField<11, 1, u32> rmwdisable;
|
||||
BitField<12, 1, Type> src_type;
|
||||
BitField<13, 1, Type> dst_type;
|
||||
BitField<14, 4, SemaphoreReduction> semaphore_reduction;
|
||||
BitField<18, 1, SemaphoreReductionSign> semaphore_reduction_sign;
|
||||
BitField<19, 1, u32> reduction_enable;
|
||||
BitField<20, 1, BypassL2> bypass_l2;
|
||||
};
|
||||
static_assert(sizeof(LaunchDMA) == 4);
|
||||
|
||||
struct RemapConst {
|
||||
enum Swizzle : u32 {
|
||||
SRC_X = 0,
|
||||
SRC_Y = 1,
|
||||
SRC_Z = 2,
|
||||
SRC_W = 3,
|
||||
CONST_A = 4,
|
||||
CONST_B = 5,
|
||||
NO_WRITE = 6,
|
||||
};
|
||||
|
||||
PackedGPUVAddr address;
|
||||
|
||||
union {
|
||||
BitField<0, 3, Swizzle> dst_x;
|
||||
BitField<4, 3, Swizzle> dst_y;
|
||||
BitField<8, 3, Swizzle> dst_z;
|
||||
BitField<12, 3, Swizzle> dst_w;
|
||||
BitField<16, 2, u32> component_size_minus_one;
|
||||
BitField<20, 2, u32> num_src_components_minus_one;
|
||||
BitField<24, 2, u32> num_dst_components_minus_one;
|
||||
};
|
||||
};
|
||||
static_assert(sizeof(RemapConst) == 12);
|
||||
|
||||
explicit MaxwellDMA(Core::System& system, MemoryManager& memory_manager);
|
||||
~MaxwellDMA() = default;
|
||||
|
||||
|
|
@ -40,144 +195,19 @@ public:
|
|||
void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
|
||||
u32 methods_pending) override;
|
||||
|
||||
struct Regs {
|
||||
static constexpr std::size_t NUM_REGS = 0x1D6;
|
||||
|
||||
struct Parameters {
|
||||
union {
|
||||
BitField<0, 4, u32> block_depth;
|
||||
BitField<4, 4, u32> block_height;
|
||||
BitField<8, 4, u32> block_width;
|
||||
};
|
||||
u32 size_x;
|
||||
u32 size_y;
|
||||
u32 size_z;
|
||||
u32 pos_z;
|
||||
union {
|
||||
BitField<0, 16, u32> pos_x;
|
||||
BitField<16, 16, u32> pos_y;
|
||||
};
|
||||
|
||||
u32 BlockHeight() const {
|
||||
return block_height.Value();
|
||||
}
|
||||
|
||||
u32 BlockDepth() const {
|
||||
return block_depth.Value();
|
||||
}
|
||||
};
|
||||
|
||||
static_assert(sizeof(Parameters) == 24, "Parameters has wrong size");
|
||||
|
||||
enum class ComponentMode : u32 {
|
||||
Src0 = 0,
|
||||
Src1 = 1,
|
||||
Src2 = 2,
|
||||
Src3 = 3,
|
||||
Const0 = 4,
|
||||
Const1 = 5,
|
||||
Zero = 6,
|
||||
};
|
||||
|
||||
enum class CopyMode : u32 {
|
||||
None = 0,
|
||||
Unk1 = 1,
|
||||
Unk2 = 2,
|
||||
};
|
||||
|
||||
enum class QueryMode : u32 {
|
||||
None = 0,
|
||||
Short = 1,
|
||||
Long = 2,
|
||||
};
|
||||
|
||||
enum class QueryIntr : u32 {
|
||||
None = 0,
|
||||
Block = 1,
|
||||
NonBlock = 2,
|
||||
};
|
||||
|
||||
union {
|
||||
struct {
|
||||
INSERT_UNION_PADDING_WORDS(0xC0);
|
||||
|
||||
struct {
|
||||
union {
|
||||
BitField<0, 2, CopyMode> copy_mode;
|
||||
BitField<2, 1, u32> flush;
|
||||
|
||||
BitField<3, 2, QueryMode> query_mode;
|
||||
BitField<5, 2, QueryIntr> query_intr;
|
||||
|
||||
BitField<7, 1, u32> is_src_linear;
|
||||
BitField<8, 1, u32> is_dst_linear;
|
||||
|
||||
BitField<9, 1, u32> enable_2d;
|
||||
BitField<10, 1, u32> enable_swizzle;
|
||||
};
|
||||
} exec;
|
||||
|
||||
INSERT_UNION_PADDING_WORDS(0x3F);
|
||||
|
||||
struct {
|
||||
u32 address_high;
|
||||
u32 address_low;
|
||||
|
||||
GPUVAddr Address() const {
|
||||
return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
|
||||
address_low);
|
||||
}
|
||||
} src_address;
|
||||
|
||||
struct {
|
||||
u32 address_high;
|
||||
u32 address_low;
|
||||
|
||||
GPUVAddr Address() const {
|
||||
return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
|
||||
address_low);
|
||||
}
|
||||
} dst_address;
|
||||
|
||||
u32 src_pitch;
|
||||
u32 dst_pitch;
|
||||
u32 x_count;
|
||||
u32 y_count;
|
||||
|
||||
INSERT_UNION_PADDING_WORDS(0xB8);
|
||||
|
||||
u32 const0;
|
||||
u32 const1;
|
||||
union {
|
||||
BitField<0, 4, ComponentMode> component0;
|
||||
BitField<4, 4, ComponentMode> component1;
|
||||
BitField<8, 4, ComponentMode> component2;
|
||||
BitField<12, 4, ComponentMode> component3;
|
||||
BitField<16, 2, u32> component_size;
|
||||
BitField<20, 3, u32> src_num_components;
|
||||
BitField<24, 3, u32> dst_num_components;
|
||||
|
||||
u32 SrcBytePerPixel() const {
|
||||
return src_num_components.Value() * component_size.Value();
|
||||
}
|
||||
u32 DstBytePerPixel() const {
|
||||
return dst_num_components.Value() * component_size.Value();
|
||||
}
|
||||
} swizzle_config;
|
||||
|
||||
Parameters dst_params;
|
||||
|
||||
INSERT_UNION_PADDING_WORDS(1);
|
||||
|
||||
Parameters src_params;
|
||||
|
||||
INSERT_UNION_PADDING_WORDS(0x13);
|
||||
};
|
||||
std::array<u32, NUM_REGS> reg_array;
|
||||
};
|
||||
} regs{};
|
||||
|
||||
private:
|
||||
/// Performs the copy from the source buffer to the destination buffer as configured in the
|
||||
/// registers.
|
||||
void Launch();
|
||||
|
||||
void CopyPitchToPitch();
|
||||
|
||||
void CopyBlockLinearToPitch();
|
||||
|
||||
void CopyPitchToBlockLinear();
|
||||
|
||||
void FastCopyBlockLinearToPitch();
|
||||
|
||||
Core::System& system;
|
||||
|
||||
MemoryManager& memory_manager;
|
||||
|
|
@ -185,28 +215,58 @@ private:
|
|||
std::vector<u8> read_buffer;
|
||||
std::vector<u8> write_buffer;
|
||||
|
||||
/// Performs the copy from the source buffer to the destination buffer as configured in the
|
||||
/// registers.
|
||||
void HandleCopy();
|
||||
static constexpr std::size_t NUM_REGS = 0x800;
|
||||
struct Regs {
|
||||
union {
|
||||
struct {
|
||||
u32 reserved[0x40];
|
||||
u32 nop;
|
||||
u32 reserved01[0xf];
|
||||
u32 pm_trigger;
|
||||
u32 reserved02[0x3f];
|
||||
Semaphore semaphore;
|
||||
u32 reserved03[0x2];
|
||||
RenderEnable render_enable;
|
||||
PhysMode src_phys_mode;
|
||||
PhysMode dst_phys_mode;
|
||||
u32 reserved04[0x26];
|
||||
LaunchDMA launch_dma;
|
||||
u32 reserved05[0x3f];
|
||||
PackedGPUVAddr offset_in;
|
||||
PackedGPUVAddr offset_out;
|
||||
u32 pitch_in;
|
||||
u32 pitch_out;
|
||||
u32 line_length_in;
|
||||
u32 line_count;
|
||||
u32 reserved06[0xb8];
|
||||
RemapConst remap_const;
|
||||
Parameters dst_params;
|
||||
u32 reserved07[0x1];
|
||||
Parameters src_params;
|
||||
u32 reserved08[0x275];
|
||||
u32 pm_trigger_end;
|
||||
u32 reserved09[0x3ba];
|
||||
};
|
||||
std::array<u32, NUM_REGS> reg_array;
|
||||
};
|
||||
} regs{};
|
||||
|
||||
#define ASSERT_REG_POSITION(field_name, position) \
|
||||
static_assert(offsetof(MaxwellDMA::Regs, field_name) == position * 4, \
|
||||
"Field " #field_name " has invalid position")
|
||||
|
||||
ASSERT_REG_POSITION(exec, 0xC0);
|
||||
ASSERT_REG_POSITION(src_address, 0x100);
|
||||
ASSERT_REG_POSITION(dst_address, 0x102);
|
||||
ASSERT_REG_POSITION(src_pitch, 0x104);
|
||||
ASSERT_REG_POSITION(dst_pitch, 0x105);
|
||||
ASSERT_REG_POSITION(x_count, 0x106);
|
||||
ASSERT_REG_POSITION(y_count, 0x107);
|
||||
ASSERT_REG_POSITION(const0, 0x1C0);
|
||||
ASSERT_REG_POSITION(const1, 0x1C1);
|
||||
ASSERT_REG_POSITION(swizzle_config, 0x1C2);
|
||||
ASSERT_REG_POSITION(launch_dma, 0xC0);
|
||||
ASSERT_REG_POSITION(offset_in, 0x100);
|
||||
ASSERT_REG_POSITION(offset_out, 0x102);
|
||||
ASSERT_REG_POSITION(pitch_in, 0x104);
|
||||
ASSERT_REG_POSITION(pitch_out, 0x105);
|
||||
ASSERT_REG_POSITION(line_length_in, 0x106);
|
||||
ASSERT_REG_POSITION(line_count, 0x107);
|
||||
ASSERT_REG_POSITION(remap_const, 0x1C0);
|
||||
ASSERT_REG_POSITION(dst_params, 0x1C3);
|
||||
ASSERT_REG_POSITION(src_params, 0x1CA);
|
||||
|
||||
#undef ASSERT_REG_POSITION
|
||||
};
|
||||
|
||||
} // namespace Tegra::Engines
|
||||
|
|
|
|||
Loading…
Reference in a new issue