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https://git.suyu.dev/suyu/suyu.git
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shader_decode: Implement TEX and TXQ
This commit is contained in:
ReinUsesLisp
parent
878672f371
commit
2b90637f4b
2 changed files with 223 additions and 0 deletions
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@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <vector>
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#include "common/assert.h"
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@ -102,6 +103,44 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::TEX: {
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Tegra::Shader::TextureType texture_type{instr.tex.texture_type};
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const bool is_array = instr.tex.array != 0;
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const bool depth_compare = instr.tex.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.tex.GetTextureProcessMode();
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UNIMPLEMENTED_IF_MSG(instr.tex.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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if (instr.tex.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TEX.NODEP is not implemented");
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}
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const Node texture = GetTexCode(instr, texture_type, process_mode, depth_compare, is_array);
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if (depth_compare) {
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SetRegister(bb, instr.gpr0, texture);
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} else {
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MetaComponents meta;
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std::array<Node, 4> dest;
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std::size_t dest_elem = 0;
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for (std::size_t elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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meta.components_map[dest_elem] = static_cast<u32>(elem);
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dest[dest_elem] = GetRegister(instr.gpr0.Value() + dest_elem);
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++dest_elem;
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}
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std::generate(dest.begin() + dest_elem, dest.end(), [&]() { return GetRegister(RZ); });
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bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta), texture,
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dest[0], dest[1], dest[2], dest[3]));
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}
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break;
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}
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case OpCode::Id::TEXS: {
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Tegra::Shader::TextureType texture_type{instr.texs.GetTextureType()};
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const bool is_array{instr.texs.IsArrayTexture()};
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@ -123,6 +162,148 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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}
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break;
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}
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case OpCode::Id::TLD4: {
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ASSERT(instr.tld4.texture_type == Tegra::Shader::TextureType::Texture2D);
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ASSERT(instr.tld4.array == 0);
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UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::NDV),
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"NDV is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::PTP),
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"PTP is not implemented");
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if (instr.tld4.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TLD4.NODEP implementation is incomplete");
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}
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const bool depth_compare = instr.tld4.UsesMiscMode(TextureMiscMode::DC);
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auto texture_type = instr.tld4.texture_type.Value();
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u32 num_coordinates = static_cast<u32>(GetCoordCount(texture_type));
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if (depth_compare)
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num_coordinates += 1;
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std::vector<Node> params;
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switch (num_coordinates) {
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case 2: {
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params.push_back(GetRegister(instr.gpr8));
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params.push_back(GetRegister(instr.gpr8.Value() + 1));
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break;
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}
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case 3: {
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params.push_back(GetRegister(instr.gpr8));
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params.push_back(GetRegister(instr.gpr8.Value() + 1));
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params.push_back(GetRegister(instr.gpr8.Value() + 2));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled coordinates number {}", static_cast<u32>(num_coordinates));
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params.push_back(GetRegister(instr.gpr8));
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params.push_back(GetRegister(instr.gpr8.Value() + 1));
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num_coordinates = 2;
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texture_type = Tegra::Shader::TextureType::Texture2D;
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}
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params.push_back(Immediate(static_cast<u32>(instr.tld4.component)));
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const auto& sampler = GetSampler(instr.sampler, texture_type, false, depth_compare);
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const MetaTexture meta{sampler, num_coordinates};
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const Node texture =
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Operation(OperationCode::F4TextureGather, std::move(meta), std::move(params));
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if (depth_compare) {
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SetRegister(bb, instr.gpr0, texture);
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} else {
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MetaComponents meta;
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std::array<Node, 4> dest;
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std::size_t dest_elem = 0;
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for (std::size_t elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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meta.components_map[dest_elem] = static_cast<u32>(elem);
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dest[dest_elem] = GetRegister(instr.gpr0.Value() + dest_elem);
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++dest_elem;
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}
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std::generate(dest.begin() + dest_elem, dest.end(), [&]() { return GetRegister(RZ); });
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bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta), texture,
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dest[0], dest[1], dest[2], dest[3]));
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}
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break;
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}
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case OpCode::Id::TLD4S: {
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UNIMPLEMENTED_IF_MSG(instr.tld4s.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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if (instr.tld4s.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TLD4S.NODEP is not implemented");
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}
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const bool depth_compare = instr.tld4s.UsesMiscMode(TextureMiscMode::DC);
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_b = GetRegister(instr.gpr20);
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std::vector<Node> params;
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// TODO(Subv): Figure out how the sampler type is encoded in the TLD4S instruction.
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if (depth_compare) {
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// Note: TLD4S coordinate encoding works just like TEXS's
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const Node op_y = GetRegister(instr.gpr8.Value() + 1);
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params.push_back(op_a);
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params.push_back(op_y);
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params.push_back(op_b);
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} else {
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params.push_back(op_a);
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params.push_back(op_b);
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}
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const auto num_coords = static_cast<u32>(params.size());
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params.push_back(Immediate(static_cast<u32>(instr.tld4s.component)));
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const auto& sampler =
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GetSampler(instr.sampler, TextureType::Texture2D, false, depth_compare);
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const MetaTexture meta{sampler, num_coords};
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WriteTexsInstructionFloat(
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bb, instr, Operation(OperationCode::F4TextureGather, meta, std::move(params)));
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break;
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}
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case OpCode::Id::TXQ: {
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if (instr.txq.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TXQ.NODEP is not implemented");
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}
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// TODO: The new commits on the texture refactor, change the way samplers work.
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// Sadly, not all texture instructions specify the type of texture their sampler
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// uses. This must be fixed at a later instance.
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const auto& sampler =
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GetSampler(instr.sampler, Tegra::Shader::TextureType::Texture2D, false, false);
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switch (instr.txq.query_type) {
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case Tegra::Shader::TextureQueryType::Dimension: {
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const MetaTexture meta_texture{sampler};
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const MetaComponents meta_components{{0, 1, 2, 3}};
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const Node texture = Operation(OperationCode::F4TextureQueryDimensions, meta_texture,
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GetRegister(instr.gpr8));
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std::array<Node, 4> dest;
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for (std::size_t i = 0; i < dest.size(); ++i) {
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dest[i] = GetRegister(instr.gpr0.Value() + i);
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}
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bb.push_back(Operation(OperationCode::AssignComposite, meta_components, texture,
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dest[0], dest[1], dest[2], dest[3]));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled texture query type: {}",
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static_cast<u32>(instr.txq.query_type.Value()));
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}
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled memory instruction: {}", opcode->get().GetName());
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}
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@ -227,6 +408,44 @@ Node ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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return Operation(read_method, meta, std::move(params));
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}
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Node ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
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TextureProcessMode process_mode, bool depth_compare, bool is_array) {
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const bool lod_bias_enabled = (process_mode != Tegra::Shader::TextureProcessMode::None &&
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process_mode != Tegra::Shader::TextureProcessMode::LZ);
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const auto [coord_count, total_coord_count] = ValidateAndGetCoordinateElement(
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texture_type, depth_compare, is_array, lod_bias_enabled, 4, 5);
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// If enabled arrays index is always stored in the gpr8 field
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const u64 array_register = instr.gpr8.Value();
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// First coordinate index is the gpr8 or gpr8 + 1 when arrays are used
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const u64 coord_register = array_register + (is_array ? 1 : 0);
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std::vector<Node> coords;
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for (std::size_t i = 0; i < coord_count; ++i) {
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coords.push_back(GetRegister(coord_register + i));
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}
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// 1D.DC in opengl the 2nd component is ignored.
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if (depth_compare && !is_array && texture_type == TextureType::Texture1D) {
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coords.push_back(Immediate(0.0f));
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}
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if (depth_compare) {
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// Depth is always stored in the register signaled by gpr20
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// or in the next register if lod or bias are used
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const u64 depth_register = instr.gpr20.Value() + (lod_bias_enabled ? 1 : 0);
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coords.push_back(GetRegister(depth_register));
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}
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if (is_array) {
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coords.push_back(GetRegister(array_register));
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}
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// Fill ignored coordinates
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while (coords.size() < total_coord_count) {
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coords.push_back(Immediate(0));
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}
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return GetTextureCode(instr, texture_type, process_mode, depth_compare, is_array, 0,
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std::move(coords));
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}
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Node ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
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TextureProcessMode process_mode, bool depth_compare, bool is_array) {
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@ -681,6 +681,10 @@ private:
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void WriteTexsInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr, Node texture);
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Node GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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bool is_array);
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Node GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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bool is_array);
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