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synced 2024-12-22 16:30:57 +01:00
ARM: Fixed several dyncom bugs.
- Fixed NZCVT flags to properly save state when function returns. - Fixed counter to keep track of the actual number of instructions executed. - Fixed single-step mode to only execute one instruction at a time. - DefaultIni: Removed comment that no longer applied to dyncom.
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4 changed files with 26 additions and 18 deletions
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@ -28,7 +28,7 @@ pad_sright =
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[Core]
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cpu_core = ## 0: Interpreter (default), 1: FastInterpreter (experimental)
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gpu_refresh_rate = ## 60 (default), 1024 or 2048 may work better on the FastInterpreter
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gpu_refresh_rate = ## 60 (default)
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[Data Storage]
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use_virtual_sd =
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@ -110,9 +110,12 @@ u64 ARM_DynCom::GetTicks() const {
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* @param num_instructions Number of instructions to executes
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*/
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void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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ticks += num_instructions;
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state->NumInstrsToExecute = num_instructions;
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InterpreterMainLoop(state.get());
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// Dyncom only breaks on instruction dispatch. This only happens on every instruction when
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// executing one instruction at a time. Otherwise, if a block is being executed, more
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// instructions may actually be executed than specified.
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ticks += InterpreterMainLoop(state.get());
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}
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/**
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@ -3718,7 +3718,7 @@ static bool InAPrivilegedMode(arm_core_t *core)
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}
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/* r15 = r15 + 8 */
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void InterpreterMainLoop(ARMul_State* state)
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unsigned InterpreterMainLoop(ARMul_State* state)
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{
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#define CRn inst_cream->crn
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#define OPCODE_2 inst_cream->opcode_2
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@ -3754,9 +3754,15 @@ void InterpreterMainLoop(ARMul_State* state)
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// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a
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// clunky switch statement.
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#if defined __GNUC__ || defined __clang__
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#define GOTO_NEXT_INST goto *InstLabel[inst_base->idx]
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#define GOTO_NEXT_INST \
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if (num_instrs >= cpu->NumInstrsToExecute) goto END; \
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num_instrs++; \
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goto *InstLabel[inst_base->idx]
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#else
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#define GOTO_NEXT_INST switch(inst_base->idx) { \
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#define GOTO_NEXT_INST \
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if (num_instrs >= cpu->NumInstrsToExecute) goto END; \
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num_instrs++; \
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switch(inst_base->idx) { \
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case 0: goto VMLA_INST; \
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case 1: goto VMLS_INST; \
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case 2: goto VNMLA_INST; \
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@ -4028,20 +4034,15 @@ void InterpreterMainLoop(ARMul_State* state)
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unsigned int addr;
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unsigned int phys_addr;
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unsigned int last_pc = 0;
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unsigned int num_instrs = 0;
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fault_t fault;
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static unsigned int last_physical_base = 0, last_logical_base = 0;
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int ptr;
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bool single_step = (cpu->NumInstrsToExecute == 1);
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LOAD_NZCVT;
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DISPATCH:
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{
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if (cpu->NumInstrsToExecute == 0)
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return;
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cpu->NumInstrsToExecute--;
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//NOTICE_LOG(ARM11, "instr!");
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if (!cpu->NirqSig) {
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if (!(cpu->Cpsr & 0x80)) {
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goto END;
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@ -4393,7 +4394,8 @@ void InterpreterMainLoop(ARMul_State* state)
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#define CP_ACCESS_ALLOW 0
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if(CP_ACCESS_ALLOW){
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/* undefined instruction here */
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return;
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cpu->NumInstrsToExecute = 0;
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return num_instrs;
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}
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ERROR_LOG(ARM11, "CDP insn inst=0x%x, pc=0x%x\n", inst_cream->inst, cpu->Reg[15]);
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unsigned cpab = (cpu->CDP[inst_cream->cp_num]) (cpu, ARMul_FIRST, inst_cream->inst);
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@ -6532,12 +6534,14 @@ void InterpreterMainLoop(ARMul_State* state)
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cpu->AbortAddr = addr;
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cpu->CP15[CP15(CP15_FAULT_STATUS)] = fault & 0xff;
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cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = addr;
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return;
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cpu->NumInstrsToExecute = 0;
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return num_instrs;
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}
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END:
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{
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SAVE_NZCVT;
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return;
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cpu->NumInstrsToExecute = 0;
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return num_instrs;
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}
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INIT_INST_LENGTH:
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{
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@ -6557,7 +6561,8 @@ void InterpreterMainLoop(ARMul_State* state)
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DEBUG_LOG(ARM11, "%llx\n", InstLabel[1]);
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DEBUG_LOG(ARM11, "%lld\n", (char *)InstEndLabel[1] - (char *)InstLabel[1]);
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#endif
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return;
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cpu->NumInstrsToExecute = 0;
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return num_instrs;
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}
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}
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@ -4,4 +4,4 @@
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#pragma once
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void InterpreterMainLoop(ARMul_State* state);
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unsigned InterpreterMainLoop(ARMul_State* state);
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