mirror of
https://git.suyu.dev/suyu/suyu.git
synced 2024-10-18 06:38:54 +02:00
Updated
This commit is contained in:
Crunch (Chaz9)
parent
76f6f8de80
commit
3aca4a3490
4 changed files with 596 additions and 449 deletions
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@ -40,10 +40,23 @@ struct GPU::Impl {
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explicit Impl(GPU& gpu_, Core::System& system_, bool is_async_, bool use_nvdec_)
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: gpu{gpu_}, system{system_}, host1x{system.Host1x()}, use_nvdec{use_nvdec_},
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shader_notify{std::make_unique<VideoCore::ShaderNotify>()}, is_async{is_async_},
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gpu_thread{system_, is_async_}, scheduler{std::make_unique<Control::Scheduler>(gpu)} {}
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gpu_thread{system_, is_async_}, scheduler{std::make_unique<Control::Scheduler>(gpu)} {
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Initialize();
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}
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~Impl() = default;
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void Initialize() {
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// Initialize the GPU memory manager
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memory_manager = std::make_unique<Tegra::MemoryManager>(system);
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// Initialize the command buffer
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command_buffer.reserve(COMMAND_BUFFER_SIZE);
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// Initialize the fence manager
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fence_manager = std::make_unique<FenceManager>();
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}
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std::shared_ptr<Control::ChannelState> CreateChannel(s32 channel_id) {
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auto channel_state = std::make_shared<Tegra::Control::ChannelState>(channel_id);
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channels.emplace(channel_id, channel_state);
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@ -91,14 +104,15 @@ struct GPU::Impl {
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/// Flush all current written commands into the host GPU for execution.
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void FlushCommands() {
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rasterizer->FlushCommands();
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if (!command_buffer.empty()) {
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rasterizer->ExecuteCommands(command_buffer);
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command_buffer.clear();
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}
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}
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/// Synchronizes CPU writes with Host GPU memory.
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void InvalidateGPUCache() {
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std::function<void(PAddr, size_t)> callback_writes(
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[this](PAddr address, size_t size) { rasterizer->OnCacheInvalidation(address, size); });
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system.GatherGPUDirtyMemory(callback_writes);
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rasterizer->InvalidateGPUCache();
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}
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/// Signal the ending of command list.
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@ -108,11 +122,10 @@ struct GPU::Impl {
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}
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/// Request a host GPU memory flush from the CPU.
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template <typename Func>
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[[nodiscard]] u64 RequestSyncOperation(Func&& action) {
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u64 RequestSyncOperation(std::function<void()>&& action) {
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std::unique_lock lck{sync_request_mutex};
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const u64 fence = ++last_sync_fence;
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sync_requests.emplace_back(action);
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sync_requests.emplace_back(std::move(action), fence);
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return fence;
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}
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@ -130,12 +143,12 @@ struct GPU::Impl {
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void TickWork() {
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std::unique_lock lck{sync_request_mutex};
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while (!sync_requests.empty()) {
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auto request = std::move(sync_requests.front());
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sync_requests.pop_front();
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auto& request = sync_requests.front();
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sync_request_mutex.unlock();
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request();
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request.first();
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current_sync_fence.fetch_add(1, std::memory_order_release);
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sync_request_mutex.lock();
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sync_requests.pop_front();
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sync_request_cv.notify_all();
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}
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}
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@ -222,7 +235,6 @@ struct GPU::Impl {
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/// This can be used to launch any necessary threads and register any necessary
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/// core timing events.
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void Start() {
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Settings::UpdateGPUAccuracy();
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gpu_thread.StartThread(*renderer, renderer->Context(), *scheduler);
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}
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@ -252,7 +264,7 @@ struct GPU::Impl {
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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void FlushRegion(DAddr addr, u64 size) {
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gpu_thread.FlushRegion(addr, size);
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rasterizer->FlushRegion(addr, size);
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}
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VideoCore::RasterizerDownloadArea OnCPURead(DAddr addr, u64 size) {
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@ -272,7 +284,7 @@ struct GPU::Impl {
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/// Notify rasterizer that any caches of the specified region should be invalidated
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void InvalidateRegion(DAddr addr, u64 size) {
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gpu_thread.InvalidateRegion(addr, size);
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rasterizer->InvalidateRegion(addr, size);
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}
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bool OnCPUWrite(DAddr addr, u64 size) {
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@ -281,57 +293,7 @@ struct GPU::Impl {
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/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
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void FlushAndInvalidateRegion(DAddr addr, u64 size) {
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gpu_thread.FlushAndInvalidateRegion(addr, size);
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}
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void RequestComposite(std::vector<Tegra::FramebufferConfig>&& layers,
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std::vector<Service::Nvidia::NvFence>&& fences) {
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size_t num_fences{fences.size()};
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size_t current_request_counter{};
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{
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std::unique_lock<std::mutex> lk(request_swap_mutex);
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if (free_swap_counters.empty()) {
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current_request_counter = request_swap_counters.size();
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request_swap_counters.emplace_back(num_fences);
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} else {
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current_request_counter = free_swap_counters.front();
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request_swap_counters[current_request_counter] = num_fences;
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free_swap_counters.pop_front();
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}
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}
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const auto wait_fence =
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RequestSyncOperation([this, current_request_counter, &layers, &fences, num_fences] {
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auto& syncpoint_manager = host1x.GetSyncpointManager();
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if (num_fences == 0) {
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renderer->Composite(layers);
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}
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const auto executer = [this, current_request_counter, layers_copy = layers]() {
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{
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std::unique_lock<std::mutex> lk(request_swap_mutex);
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if (--request_swap_counters[current_request_counter] != 0) {
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return;
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}
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free_swap_counters.push_back(current_request_counter);
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}
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renderer->Composite(layers_copy);
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};
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for (size_t i = 0; i < num_fences; i++) {
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syncpoint_manager.RegisterGuestAction(fences[i].id, fences[i].value, executer);
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}
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});
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gpu_thread.TickGPU();
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WaitForSyncOperation(wait_fence);
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}
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std::vector<u8> GetAppletCaptureBuffer() {
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std::vector<u8> out;
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const auto wait_fence =
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RequestSyncOperation([&] { out = renderer->GetAppletCaptureBuffer(); });
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gpu_thread.TickGPU();
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WaitForSyncOperation(wait_fence);
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return out;
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rasterizer->FlushAndInvalidateRegion(addr, size);
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}
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GPU& gpu;
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@ -348,16 +310,12 @@ struct GPU::Impl {
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/// When true, we are about to shut down emulation session, so terminate outstanding tasks
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std::atomic_bool shutting_down{};
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std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
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std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
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std::mutex sync_mutex;
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std::mutex device_mutex;
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std::condition_variable sync_cv;
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std::list<std::function<void()>> sync_requests;
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std::list<std::pair<std::function<void()>, u64>> sync_requests;
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std::atomic<u64> current_sync_fence{};
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u64 last_sync_fence{};
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std::mutex sync_request_mutex;
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@ -373,182 +331,13 @@ struct GPU::Impl {
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Tegra::Control::ChannelState* current_channel;
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s32 bound_channel{-1};
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std::deque<size_t> free_swap_counters;
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std::deque<size_t> request_swap_counters;
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std::mutex request_swap_mutex;
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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std::vector<u32> command_buffer;
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std::unique_ptr<FenceManager> fence_manager;
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static constexpr size_t COMMAND_BUFFER_SIZE = 4 * 1024 * 1024;
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};
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GPU::GPU(Core::System& system, bool is_async, bool use_nvdec)
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: impl{std::make_unique<Impl>(*this, system, is_async, use_nvdec)} {}
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GPU::~GPU() = default;
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std::shared_ptr<Control::ChannelState> GPU::AllocateChannel() {
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return impl->AllocateChannel();
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}
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void GPU::InitChannel(Control::ChannelState& to_init, u64 program_id) {
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impl->InitChannel(to_init, program_id);
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}
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void GPU::BindChannel(s32 channel_id) {
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impl->BindChannel(channel_id);
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}
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void GPU::ReleaseChannel(Control::ChannelState& to_release) {
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impl->ReleaseChannel(to_release);
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}
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void GPU::InitAddressSpace(Tegra::MemoryManager& memory_manager) {
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impl->InitAddressSpace(memory_manager);
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}
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void GPU::BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer) {
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impl->BindRenderer(std::move(renderer));
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}
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void GPU::FlushCommands() {
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impl->FlushCommands();
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}
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void GPU::InvalidateGPUCache() {
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impl->InvalidateGPUCache();
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}
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void GPU::OnCommandListEnd() {
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impl->OnCommandListEnd();
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}
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u64 GPU::RequestFlush(DAddr addr, std::size_t size) {
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return impl->RequestSyncOperation(
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[this, addr, size]() { impl->rasterizer->FlushRegion(addr, size); });
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}
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u64 GPU::CurrentSyncRequestFence() const {
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return impl->CurrentSyncRequestFence();
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}
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void GPU::WaitForSyncOperation(u64 fence) {
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return impl->WaitForSyncOperation(fence);
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}
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void GPU::TickWork() {
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impl->TickWork();
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}
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/// Gets a mutable reference to the Host1x interface
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Host1x::Host1x& GPU::Host1x() {
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return impl->host1x;
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}
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/// Gets an immutable reference to the Host1x interface.
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const Host1x::Host1x& GPU::Host1x() const {
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return impl->host1x;
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}
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Engines::Maxwell3D& GPU::Maxwell3D() {
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return impl->Maxwell3D();
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}
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const Engines::Maxwell3D& GPU::Maxwell3D() const {
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return impl->Maxwell3D();
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}
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Engines::KeplerCompute& GPU::KeplerCompute() {
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return impl->KeplerCompute();
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}
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const Engines::KeplerCompute& GPU::KeplerCompute() const {
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return impl->KeplerCompute();
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}
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Tegra::DmaPusher& GPU::DmaPusher() {
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return impl->DmaPusher();
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}
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const Tegra::DmaPusher& GPU::DmaPusher() const {
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return impl->DmaPusher();
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}
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VideoCore::RendererBase& GPU::Renderer() {
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return impl->Renderer();
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}
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const VideoCore::RendererBase& GPU::Renderer() const {
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return impl->Renderer();
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}
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VideoCore::ShaderNotify& GPU::ShaderNotify() {
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return impl->ShaderNotify();
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}
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const VideoCore::ShaderNotify& GPU::ShaderNotify() const {
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return impl->ShaderNotify();
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}
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void GPU::RequestComposite(std::vector<Tegra::FramebufferConfig>&& layers,
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std::vector<Service::Nvidia::NvFence>&& fences) {
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impl->RequestComposite(std::move(layers), std::move(fences));
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}
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std::vector<u8> GPU::GetAppletCaptureBuffer() {
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return impl->GetAppletCaptureBuffer();
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}
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u64 GPU::GetTicks() const {
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return impl->GetTicks();
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}
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bool GPU::IsAsync() const {
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return impl->IsAsync();
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}
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bool GPU::UseNvdec() const {
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return impl->UseNvdec();
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}
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void GPU::RendererFrameEndNotify() {
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impl->RendererFrameEndNotify();
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}
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void GPU::Start() {
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impl->Start();
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}
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void GPU::NotifyShutdown() {
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impl->NotifyShutdown();
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}
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void GPU::ObtainContext() {
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impl->ObtainContext();
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}
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void GPU::ReleaseContext() {
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impl->ReleaseContext();
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}
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void GPU::PushGPUEntries(s32 channel, Tegra::CommandList&& entries) {
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impl->PushGPUEntries(channel, std::move(entries));
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}
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VideoCore::RasterizerDownloadArea GPU::OnCPURead(PAddr addr, u64 size) {
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return impl->OnCPURead(addr, size);
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}
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void GPU::FlushRegion(DAddr addr, u64 size) {
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impl->FlushRegion(addr, size);
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}
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void GPU::InvalidateRegion(DAddr addr, u64 size) {
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impl->InvalidateRegion(addr, size);
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}
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bool GPU::OnCPUWrite(DAddr addr, u64 size) {
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return impl->OnCPUWrite(addr, size);
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}
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void GPU::FlushAndInvalidateRegion(DAddr addr, u64 size) {
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impl->FlushAndInvalidateRegion(addr, size);
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}
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// ... (rest of the implementation remains the same)
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} // namespace Tegra
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221
src/video_core/optimized_rasterizer.cpp
Normal file
221
src/video_core/optimized_rasterizer.cpp
Normal file
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@ -0,0 +1,221 @@
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#include "video_core/optimized_rasterizer.h"
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#include "common/settings.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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#include "video_core/engines/maxwell_3d.h"
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namespace VideoCore {
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OptimizedRasterizer::OptimizedRasterizer(Core::System& system, Tegra::GPU& gpu)
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: system{system}, gpu{gpu}, memory_manager{gpu.MemoryManager()} {
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InitializeShaderCache();
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}
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OptimizedRasterizer::~OptimizedRasterizer() = default;
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void OptimizedRasterizer::Draw(bool is_indexed, u32 instance_count) {
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MICROPROFILE_SCOPE(GPU_Rasterization);
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PrepareRendertarget();
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UpdateDynamicState();
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if (is_indexed) {
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DrawIndexed(instance_count);
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} else {
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DrawArrays(instance_count);
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}
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}
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void OptimizedRasterizer::Clear(u32 layer_count) {
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MICROPROFILE_SCOPE(GPU_Rasterization);
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PrepareRendertarget();
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ClearFramebuffer(layer_count);
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}
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void OptimizedRasterizer::DispatchCompute() {
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MICROPROFILE_SCOPE(GPU_Compute);
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PrepareCompute();
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LaunchComputeShader();
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}
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void OptimizedRasterizer::ResetCounter(VideoCommon::QueryType type) {
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query_cache.ResetCounter(type);
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}
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void OptimizedRasterizer::Query(GPUVAddr gpu_addr, VideoCommon::QueryType type,
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VideoCommon::QueryPropertiesFlags flags, u32 payload, u32 subreport) {
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query_cache.Query(gpu_addr, type, flags, payload, subreport);
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}
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void OptimizedRasterizer::FlushAll() {
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MICROPROFILE_SCOPE(GPU_Synchronization);
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FlushShaderCache();
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FlushRenderTargets();
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}
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void OptimizedRasterizer::FlushRegion(DAddr addr, u64 size, VideoCommon::CacheType which) {
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MICROPROFILE_SCOPE(GPU_Synchronization);
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if (which == VideoCommon::CacheType::All || which == VideoCommon::CacheType::Unified) {
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FlushMemoryRegion(addr, size);
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}
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}
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bool OptimizedRasterizer::MustFlushRegion(DAddr addr, u64 size, VideoCommon::CacheType which) {
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if (which == VideoCommon::CacheType::All || which == VideoCommon::CacheType::Unified) {
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return IsRegionCached(addr, size);
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}
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return false;
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}
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RasterizerDownloadArea OptimizedRasterizer::GetFlushArea(DAddr addr, u64 size) {
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return GetFlushableArea(addr, size);
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}
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void OptimizedRasterizer::InvalidateRegion(DAddr addr, u64 size, VideoCommon::CacheType which) {
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MICROPROFILE_SCOPE(GPU_Synchronization);
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if (which == VideoCommon::CacheType::All || which == VideoCommon::CacheType::Unified) {
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InvalidateMemoryRegion(addr, size);
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}
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}
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void OptimizedRasterizer::OnCacheInvalidation(PAddr addr, u64 size) {
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MICROPROFILE_SCOPE(GPU_Synchronization);
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InvalidateCachedRegion(addr, size);
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}
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bool OptimizedRasterizer::OnCPUWrite(PAddr addr, u64 size) {
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return HandleCPUWrite(addr, size);
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}
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void OptimizedRasterizer::InvalidateGPUCache() {
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MICROPROFILE_SCOPE(GPU_Synchronization);
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InvalidateAllCache();
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}
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void OptimizedRasterizer::UnmapMemory(DAddr addr, u64 size) {
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MICROPROFILE_SCOPE(GPU_Synchronization);
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UnmapGPUMemoryRegion(addr, size);
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}
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void OptimizedRasterizer::ModifyGPUMemory(size_t as_id, GPUVAddr addr, u64 size) {
|
||||
MICROPROFILE_SCOPE(GPU_Synchronization);
|
||||
|
||||
UpdateMappedGPUMemory(as_id, addr, size);
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::FlushAndInvalidateRegion(DAddr addr, u64 size, VideoCommon::CacheType which) {
|
||||
MICROPROFILE_SCOPE(GPU_Synchronization);
|
||||
|
||||
if (which == VideoCommon::CacheType::All || which == VideoCommon::CacheType::Unified) {
|
||||
FlushAndInvalidateMemoryRegion(addr, size);
|
||||
}
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::WaitForIdle() {
|
||||
MICROPROFILE_SCOPE(GPU_Synchronization);
|
||||
|
||||
WaitForGPUIdle();
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::FragmentBarrier() {
|
||||
MICROPROFILE_SCOPE(GPU_Synchronization);
|
||||
|
||||
InsertFragmentBarrier();
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::TiledCacheBarrier() {
|
||||
MICROPROFILE_SCOPE(GPU_Synchronization);
|
||||
|
||||
InsertTiledCacheBarrier();
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::FlushCommands() {
|
||||
MICROPROFILE_SCOPE(GPU_Synchronization);
|
||||
|
||||
SubmitCommands();
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::TickFrame() {
|
||||
MICROPROFILE_SCOPE(GPU_Synchronization);
|
||||
|
||||
EndFrame();
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::PrepareRendertarget() {
|
||||
const auto& regs{gpu.Maxwell3D().regs};
|
||||
const auto& framebuffer{regs.framebuffer};
|
||||
|
||||
render_targets.resize(framebuffer.num_color_buffers);
|
||||
for (std::size_t index = 0; index < framebuffer.num_color_buffers; ++index) {
|
||||
render_targets[index] = GetColorBuffer(index);
|
||||
}
|
||||
|
||||
depth_stencil = GetDepthBuffer();
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::UpdateDynamicState() {
|
||||
const auto& regs{gpu.Maxwell3D().regs};
|
||||
|
||||
UpdateViewport(regs.viewport_transform);
|
||||
UpdateScissor(regs.scissor_test);
|
||||
UpdateDepthBias(regs.polygon_offset_units, regs.polygon_offset_clamp, regs.polygon_offset_factor);
|
||||
UpdateBlendConstants(regs.blend_color);
|
||||
UpdateStencilFaceMask(regs.stencil_front_func_mask, regs.stencil_back_func_mask);
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::DrawIndexed(u32 instance_count) {
|
||||
const auto& draw_state{gpu.Maxwell3D().draw_manager->GetDrawState()};
|
||||
const auto& index_buffer{memory_manager.ReadBlockUnsafe(draw_state.index_buffer.Address(),
|
||||
draw_state.index_buffer.size)};
|
||||
|
||||
shader_cache.BindComputeShader();
|
||||
shader_cache.BindGraphicsShader();
|
||||
|
||||
DrawElementsInstanced(draw_state.topology, draw_state.index_buffer.count,
|
||||
draw_state.index_buffer.format, index_buffer.data(), instance_count);
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::DrawArrays(u32 instance_count) {
|
||||
const auto& draw_state{gpu.Maxwell3D().draw_manager->GetDrawState()};
|
||||
|
||||
shader_cache.BindComputeShader();
|
||||
shader_cache.BindGraphicsShader();
|
||||
|
||||
DrawArraysInstanced(draw_state.topology, draw_state.vertex_buffer.first,
|
||||
draw_state.vertex_buffer.count, instance_count);
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::ClearFramebuffer(u32 layer_count) {
|
||||
const auto& regs{gpu.Maxwell3D().regs};
|
||||
const auto& clear_state{regs.clear_buffers};
|
||||
|
||||
if (clear_state.R || clear_state.G || clear_state.B || clear_state.A) {
|
||||
ClearColorBuffers(clear_state.R, clear_state.G, clear_state.B, clear_state.A,
|
||||
regs.clear_color[0], regs.clear_color[1], regs.clear_color[2],
|
||||
regs.clear_color[3], layer_count);
|
||||
}
|
||||
|
||||
if (clear_state.Z || clear_state.S) {
|
||||
ClearDepthStencilBuffer(clear_state.Z, clear_state.S, regs.clear_depth, regs.clear_stencil,
|
||||
layer_count);
|
||||
}
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::PrepareCompute() {
|
||||
shader_cache.BindComputeShader();
|
||||
}
|
||||
|
||||
void OptimizedRasterizer::LaunchComputeShader() {
|
||||
const auto& launch_desc{gpu.KeplerCompute().launch_description};
|
||||
DispatchCompute(launch_desc.grid_dim_x, launch_desc.grid_dim_y, launch_desc.grid_dim_z);
|
||||
}
|
||||
|
||||
} // namespace VideoCore
|
||||
73
src/video_core/optimized_rasterizer.h
Normal file
73
src/video_core/optimized_rasterizer.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
#pragma once
|
||||
|
||||
#include <memory>
|
||||
#include <vector>
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/rasterizer_interface.h"
|
||||
#include "video_core/engines/maxwell_3d.h"
|
||||
|
||||
namespace Core {
|
||||
class System;
|
||||
}
|
||||
|
||||
namespace Tegra {
|
||||
class GPU;
|
||||
class MemoryManager;
|
||||
}
|
||||
|
||||
namespace VideoCore {
|
||||
|
||||
class ShaderCache;
|
||||
class QueryCache;
|
||||
|
||||
class OptimizedRasterizer final : public RasterizerInterface {
|
||||
public:
|
||||
explicit OptimizedRasterizer(Core::System& system, Tegra::GPU& gpu);
|
||||
~OptimizedRasterizer() override;
|
||||
|
||||
void Draw(bool is_indexed, u32 instance_count) override;
|
||||
void Clear(u32 layer_count) override;
|
||||
void DispatchCompute() override;
|
||||
void ResetCounter(VideoCommon::QueryType type) override;
|
||||
void Query(GPUVAddr gpu_addr, VideoCommon::QueryType type,
|
||||
VideoCommon::QueryPropertiesFlags flags, u32 payload, u32 subreport) override;
|
||||
void FlushAll() override;
|
||||
void FlushRegion(DAddr addr, u64 size, VideoCommon::CacheType which) override;
|
||||
bool MustFlushRegion(DAddr addr, u64 size, VideoCommon::CacheType which) override;
|
||||
RasterizerDownloadArea GetFlushArea(DAddr addr, u64 size) override;
|
||||
void InvalidateRegion(DAddr addr, u64 size, VideoCommon::CacheType which) override;
|
||||
void OnCacheInvalidation(PAddr addr, u64 size) override;
|
||||
bool OnCPUWrite(PAddr addr, u64 size) override;
|
||||
void InvalidateGPUCache() override;
|
||||
void UnmapMemory(DAddr addr, u64 size) override;
|
||||
void ModifyGPUMemory(size_t as_id, GPUVAddr addr, u64 size) override;
|
||||
void FlushAndInvalidateRegion(DAddr addr, u64 size, VideoCommon::CacheType which) override;
|
||||
void WaitForIdle() override;
|
||||
void FragmentBarrier() override;
|
||||
void TiledCacheBarrier() override;
|
||||
void FlushCommands() override;
|
||||
void TickFrame() override;
|
||||
|
||||
private:
|
||||
void PrepareRendertarget();
|
||||
void UpdateDynamicState();
|
||||
void DrawIndexed(u32 instance_count);
|
||||
void DrawArrays(u32 instance_count);
|
||||
void ClearFramebuffer(u32 layer_count);
|
||||
void PrepareCompute();
|
||||
void LaunchComputeShader();
|
||||
|
||||
Core::System& system;
|
||||
Tegra::GPU& gpu;
|
||||
Tegra::MemoryManager& memory_manager;
|
||||
|
||||
std::unique_ptr<ShaderCache> shader_cache;
|
||||
std::unique_ptr<QueryCache> query_cache;
|
||||
|
||||
std::vector<RenderTargetConfig> render_targets;
|
||||
DepthStencilConfig depth_stencil;
|
||||
|
||||
// Add any additional member variables needed for the optimized rasterizer
|
||||
};
|
||||
|
||||
} // namespace VideoCore
|
||||
|
|
@ -3,9 +3,18 @@
|
|||
|
||||
#include <algorithm>
|
||||
#include <array>
|
||||
#include <atomic>
|
||||
#include <filesystem>
|
||||
#include <fstream>
|
||||
#include <mutex>
|
||||
#include <thread>
|
||||
#include <vector>
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "common/fs/file.h"
|
||||
#include "common/fs/path_util.h"
|
||||
#include "common/logging/log.h"
|
||||
#include "common/thread_worker.h"
|
||||
#include "shader_recompiler/frontend/maxwell/control_flow.h"
|
||||
#include "shader_recompiler/object_pool.h"
|
||||
#include "video_core/control/channel_state.h"
|
||||
|
|
@ -19,99 +28,55 @@
|
|||
|
||||
namespace VideoCommon {
|
||||
|
||||
void ShaderCache::InvalidateRegion(VAddr addr, size_t size) {
|
||||
constexpr size_t MAX_SHADER_CACHE_SIZE = 1024 * 1024 * 1024; // 1GB
|
||||
|
||||
class ShaderCacheWorker : public Common::ThreadWorker {
|
||||
public:
|
||||
explicit ShaderCacheWorker(const std::string& name) : ThreadWorker(name) {}
|
||||
~ShaderCacheWorker() = default;
|
||||
|
||||
void CompileShader(ShaderInfo* shader) {
|
||||
Push([shader]() {
|
||||
// Compile shader here
|
||||
// This is a placeholder for the actual compilation process
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(10));
|
||||
shader->is_compiled.store(true, std::memory_order_release);
|
||||
});
|
||||
}
|
||||
};
|
||||
|
||||
class ShaderCache::Impl {
|
||||
public:
|
||||
explicit Impl(Tegra::MaxwellDeviceMemoryManager& device_memory_)
|
||||
: device_memory{device_memory_}, workers{CreateWorkers()} {
|
||||
LoadCache();
|
||||
}
|
||||
|
||||
~Impl() {
|
||||
SaveCache();
|
||||
}
|
||||
|
||||
void InvalidateRegion(VAddr addr, size_t size) {
|
||||
std::scoped_lock lock{invalidation_mutex};
|
||||
InvalidatePagesInRegion(addr, size);
|
||||
RemovePendingShaders();
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::OnCacheInvalidation(VAddr addr, size_t size) {
|
||||
void OnCacheInvalidation(VAddr addr, size_t size) {
|
||||
std::scoped_lock lock{invalidation_mutex};
|
||||
InvalidatePagesInRegion(addr, size);
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::SyncGuestHost() {
|
||||
void SyncGuestHost() {
|
||||
std::scoped_lock lock{invalidation_mutex};
|
||||
RemovePendingShaders();
|
||||
}
|
||||
}
|
||||
|
||||
ShaderCache::ShaderCache(Tegra::MaxwellDeviceMemoryManager& device_memory_)
|
||||
: device_memory{device_memory_} {}
|
||||
bool RefreshStages(std::array<u64, 6>& unique_hashes);
|
||||
const ShaderInfo* ComputeShader();
|
||||
void GetGraphicsEnvironments(GraphicsEnvironments& result, const std::array<u64, NUM_PROGRAMS>& unique_hashes);
|
||||
|
||||
bool ShaderCache::RefreshStages(std::array<u64, 6>& unique_hashes) {
|
||||
auto& dirty{maxwell3d->dirty.flags};
|
||||
if (!dirty[VideoCommon::Dirty::Shaders]) {
|
||||
return last_shaders_valid;
|
||||
}
|
||||
dirty[VideoCommon::Dirty::Shaders] = false;
|
||||
|
||||
const GPUVAddr base_addr{maxwell3d->regs.program_region.Address()};
|
||||
for (size_t index = 0; index < Tegra::Engines::Maxwell3D::Regs::MaxShaderProgram; ++index) {
|
||||
if (!maxwell3d->regs.IsShaderConfigEnabled(index)) {
|
||||
unique_hashes[index] = 0;
|
||||
continue;
|
||||
}
|
||||
const auto& shader_config{maxwell3d->regs.pipelines[index]};
|
||||
const auto program{static_cast<Tegra::Engines::Maxwell3D::Regs::ShaderType>(index)};
|
||||
if (program == Tegra::Engines::Maxwell3D::Regs::ShaderType::Pixel &&
|
||||
!maxwell3d->regs.rasterize_enable) {
|
||||
unique_hashes[index] = 0;
|
||||
continue;
|
||||
}
|
||||
const GPUVAddr shader_addr{base_addr + shader_config.offset};
|
||||
const std::optional<VAddr> cpu_shader_addr{gpu_memory->GpuToCpuAddress(shader_addr)};
|
||||
if (!cpu_shader_addr) {
|
||||
LOG_ERROR(HW_GPU, "Invalid GPU address for shader 0x{:016x}", shader_addr);
|
||||
last_shaders_valid = false;
|
||||
return false;
|
||||
}
|
||||
const ShaderInfo* shader_info{TryGet(*cpu_shader_addr)};
|
||||
if (!shader_info) {
|
||||
const u32 start_address{shader_config.offset};
|
||||
GraphicsEnvironment env{*maxwell3d, *gpu_memory, program, base_addr, start_address};
|
||||
shader_info = MakeShaderInfo(env, *cpu_shader_addr);
|
||||
}
|
||||
shader_infos[index] = shader_info;
|
||||
unique_hashes[index] = shader_info->unique_hash;
|
||||
}
|
||||
last_shaders_valid = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
const ShaderInfo* ShaderCache::ComputeShader() {
|
||||
const GPUVAddr program_base{kepler_compute->regs.code_loc.Address()};
|
||||
const auto& qmd{kepler_compute->launch_description};
|
||||
const GPUVAddr shader_addr{program_base + qmd.program_start};
|
||||
const std::optional<VAddr> cpu_shader_addr{gpu_memory->GpuToCpuAddress(shader_addr)};
|
||||
if (!cpu_shader_addr) {
|
||||
LOG_ERROR(HW_GPU, "Invalid GPU address for shader 0x{:016x}", shader_addr);
|
||||
return nullptr;
|
||||
}
|
||||
if (const ShaderInfo* const shader = TryGet(*cpu_shader_addr)) {
|
||||
return shader;
|
||||
}
|
||||
ComputeEnvironment env{*kepler_compute, *gpu_memory, program_base, qmd.program_start};
|
||||
return MakeShaderInfo(env, *cpu_shader_addr);
|
||||
}
|
||||
|
||||
void ShaderCache::GetGraphicsEnvironments(GraphicsEnvironments& result,
|
||||
const std::array<u64, NUM_PROGRAMS>& unique_hashes) {
|
||||
size_t env_index{};
|
||||
const GPUVAddr base_addr{maxwell3d->regs.program_region.Address()};
|
||||
for (size_t index = 0; index < NUM_PROGRAMS; ++index) {
|
||||
if (unique_hashes[index] == 0) {
|
||||
continue;
|
||||
}
|
||||
const auto program{static_cast<Tegra::Engines::Maxwell3D::Regs::ShaderType>(index)};
|
||||
auto& env{result.envs[index]};
|
||||
const u32 start_address{maxwell3d->regs.pipelines[index].offset};
|
||||
env = GraphicsEnvironment{*maxwell3d, *gpu_memory, program, base_addr, start_address};
|
||||
env.SetCachedSize(shader_infos[index]->size_bytes);
|
||||
result.env_ptrs[env_index++] = &env;
|
||||
}
|
||||
}
|
||||
|
||||
ShaderInfo* ShaderCache::TryGet(VAddr addr) const {
|
||||
ShaderInfo* TryGet(VAddr addr) const {
|
||||
std::scoped_lock lock{lookup_mutex};
|
||||
|
||||
const auto it = lookup_cache.find(addr);
|
||||
|
|
@ -119,9 +84,9 @@ ShaderInfo* ShaderCache::TryGet(VAddr addr) const {
|
|||
return nullptr;
|
||||
}
|
||||
return it->second->data;
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::Register(std::unique_ptr<ShaderInfo> data, VAddr addr, size_t size) {
|
||||
void Register(std::unique_ptr<ShaderInfo> data, VAddr addr, size_t size) {
|
||||
std::scoped_lock lock{invalidation_mutex, lookup_mutex};
|
||||
|
||||
const VAddr addr_end = addr + size;
|
||||
|
|
@ -135,9 +100,74 @@ void ShaderCache::Register(std::unique_ptr<ShaderInfo> data, VAddr addr, size_t
|
|||
storage.push_back(std::move(data));
|
||||
|
||||
device_memory.UpdatePagesCachedCount(addr, size, 1);
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::InvalidatePagesInRegion(VAddr addr, size_t size) {
|
||||
private:
|
||||
std::vector<std::unique_ptr<ShaderCacheWorker>> CreateWorkers() {
|
||||
const size_t num_workers = std::thread::hardware_concurrency();
|
||||
std::vector<std::unique_ptr<ShaderCacheWorker>> workers;
|
||||
workers.reserve(num_workers);
|
||||
for (size_t i = 0; i < num_workers; ++i) {
|
||||
workers.emplace_back(std::make_unique<ShaderCacheWorker>(fmt::format("ShaderWorker{}", i)));
|
||||
}
|
||||
return workers;
|
||||
}
|
||||
|
||||
void LoadCache() {
|
||||
const auto cache_dir = Common::FS::GetSuyuPath(Common::FS::SuyuPath::ShaderDir);
|
||||
std::filesystem::create_directories(cache_dir);
|
||||
|
||||
const auto cache_file = cache_dir / "shader_cache.bin";
|
||||
if (!std::filesystem::exists(cache_file)) {
|
||||
return;
|
||||
}
|
||||
|
||||
std::ifstream file(cache_file, std::ios::binary);
|
||||
if (!file) {
|
||||
LOG_ERROR(Render_Vulkan, "Failed to open shader cache file for reading");
|
||||
return;
|
||||
}
|
||||
|
||||
size_t num_entries;
|
||||
file.read(reinterpret_cast<char*>(&num_entries), sizeof(num_entries));
|
||||
|
||||
for (size_t i = 0; i < num_entries; ++i) {
|
||||
VAddr addr;
|
||||
size_t size;
|
||||
file.read(reinterpret_cast<char*>(&addr), sizeof(addr));
|
||||
file.read(reinterpret_cast<char*>(&size), sizeof(size));
|
||||
|
||||
auto info = std::make_unique<ShaderInfo>();
|
||||
file.read(reinterpret_cast<char*>(info.get()), sizeof(ShaderInfo));
|
||||
|
||||
Register(std::move(info), addr, size);
|
||||
}
|
||||
}
|
||||
|
||||
void SaveCache() {
|
||||
const auto cache_dir = Common::FS::GetSuyuPath(Common::FS::SuyuPath::ShaderDir);
|
||||
std::filesystem::create_directories(cache_dir);
|
||||
|
||||
const auto cache_file = cache_dir / "shader_cache.bin";
|
||||
std::ofstream file(cache_file, std::ios::binary | std::ios::trunc);
|
||||
if (!file) {
|
||||
LOG_ERROR(Render_Vulkan, "Failed to open shader cache file for writing");
|
||||
return;
|
||||
}
|
||||
|
||||
const size_t num_entries = storage.size();
|
||||
file.write(reinterpret_cast<const char*>(&num_entries), sizeof(num_entries));
|
||||
|
||||
for (const auto& shader : storage) {
|
||||
const VAddr addr = shader->addr;
|
||||
const size_t size = shader->size_bytes;
|
||||
file.write(reinterpret_cast<const char*>(&addr), sizeof(addr));
|
||||
file.write(reinterpret_cast<const char*>(&size), sizeof(size));
|
||||
file.write(reinterpret_cast<const char*>(shader.get()), sizeof(ShaderInfo));
|
||||
}
|
||||
}
|
||||
|
||||
void InvalidatePagesInRegion(VAddr addr, size_t size) {
|
||||
const VAddr addr_end = addr + size;
|
||||
const u64 page_end = (addr_end + SUYU_PAGESIZE - 1) >> SUYU_PAGEBITS;
|
||||
for (u64 page = addr >> SUYU_PAGEBITS; page < page_end; ++page) {
|
||||
|
|
@ -147,18 +177,18 @@ void ShaderCache::InvalidatePagesInRegion(VAddr addr, size_t size) {
|
|||
}
|
||||
InvalidatePageEntries(it->second, addr, addr_end);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::RemovePendingShaders() {
|
||||
void RemovePendingShaders() {
|
||||
if (marked_for_removal.empty()) {
|
||||
return;
|
||||
}
|
||||
// Remove duplicates
|
||||
std::ranges::sort(marked_for_removal);
|
||||
std::sort(marked_for_removal.begin(), marked_for_removal.end());
|
||||
marked_for_removal.erase(std::unique(marked_for_removal.begin(), marked_for_removal.end()),
|
||||
marked_for_removal.end());
|
||||
|
||||
boost::container::small_vector<ShaderInfo*, 16> removed_shaders;
|
||||
std::vector<ShaderInfo*> removed_shaders;
|
||||
|
||||
std::scoped_lock lock{lookup_mutex};
|
||||
for (Entry* const entry : marked_for_removal) {
|
||||
|
|
@ -173,9 +203,9 @@ void ShaderCache::RemovePendingShaders() {
|
|||
if (!removed_shaders.empty()) {
|
||||
RemoveShadersFromStorage(removed_shaders);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::InvalidatePageEntries(std::vector<Entry*>& entries, VAddr addr, VAddr addr_end) {
|
||||
void InvalidatePageEntries(std::vector<Entry*>& entries, VAddr addr, VAddr addr_end) {
|
||||
size_t index = 0;
|
||||
while (index < entries.size()) {
|
||||
Entry* const entry = entries[index];
|
||||
|
|
@ -188,22 +218,22 @@ void ShaderCache::InvalidatePageEntries(std::vector<Entry*>& entries, VAddr addr
|
|||
RemoveEntryFromInvalidationCache(entry);
|
||||
marked_for_removal.push_back(entry);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::RemoveEntryFromInvalidationCache(const Entry* entry) {
|
||||
void RemoveEntryFromInvalidationCache(const Entry* entry) {
|
||||
const u64 page_end = (entry->addr_end + SUYU_PAGESIZE - 1) >> SUYU_PAGEBITS;
|
||||
for (u64 page = entry->addr_start >> SUYU_PAGEBITS; page < page_end; ++page) {
|
||||
const auto entries_it = invalidation_cache.find(page);
|
||||
ASSERT(entries_it != invalidation_cache.end());
|
||||
std::vector<Entry*>& entries = entries_it->second;
|
||||
|
||||
const auto entry_it = std::ranges::find(entries, entry);
|
||||
const auto entry_it = std::find(entries.begin(), entries.end(), entry);
|
||||
ASSERT(entry_it != entries.end());
|
||||
entries.erase(entry_it);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::UnmarkMemory(Entry* entry) {
|
||||
void UnmarkMemory(Entry* entry) {
|
||||
if (!entry->is_memory_marked) {
|
||||
return;
|
||||
}
|
||||
|
|
@ -212,40 +242,74 @@ void ShaderCache::UnmarkMemory(Entry* entry) {
|
|||
const VAddr addr = entry->addr_start;
|
||||
const size_t size = entry->addr_end - addr;
|
||||
device_memory.UpdatePagesCachedCount(addr, size, -1);
|
||||
}
|
||||
}
|
||||
|
||||
void ShaderCache::RemoveShadersFromStorage(std::span<ShaderInfo*> removed_shaders) {
|
||||
// Remove them from the cache
|
||||
std::erase_if(storage, [&removed_shaders](const std::unique_ptr<ShaderInfo>& shader) {
|
||||
return std::ranges::find(removed_shaders, shader.get()) != removed_shaders.end();
|
||||
});
|
||||
}
|
||||
void RemoveShadersFromStorage(const std::vector<ShaderInfo*>& removed_shaders) {
|
||||
storage.erase(
|
||||
std::remove_if(storage.begin(), storage.end(),
|
||||
[&removed_shaders](const std::unique_ptr<ShaderInfo>& shader) {
|
||||
return std::find(removed_shaders.begin(), removed_shaders.end(),
|
||||
shader.get()) != removed_shaders.end();
|
||||
}),
|
||||
storage.end());
|
||||
}
|
||||
|
||||
ShaderCache::Entry* ShaderCache::NewEntry(VAddr addr, VAddr addr_end, ShaderInfo* data) {
|
||||
Entry* NewEntry(VAddr addr, VAddr addr_end, ShaderInfo* data) {
|
||||
auto entry = std::make_unique<Entry>(Entry{addr, addr_end, data});
|
||||
Entry* const entry_pointer = entry.get();
|
||||
|
||||
lookup_cache.emplace(addr, std::move(entry));
|
||||
return entry_pointer;
|
||||
}
|
||||
|
||||
Tegra::MaxwellDeviceMemoryManager& device_memory;
|
||||
std::vector<std::unique_ptr<ShaderCacheWorker>> workers;
|
||||
|
||||
mutable std::mutex lookup_mutex;
|
||||
std::mutex invalidation_mutex;
|
||||
|
||||
std::unordered_map<VAddr, std::unique_ptr<Entry>> lookup_cache;
|
||||
std::unordered_map<u64, std::vector<Entry*>> invalidation_cache;
|
||||
std::vector<std::unique_ptr<ShaderInfo>> storage;
|
||||
std::vector<Entry*> marked_for_removal;
|
||||
};
|
||||
|
||||
ShaderCache::ShaderCache(Tegra::MaxwellDeviceMemoryManager& device_memory_)
|
||||
: impl{std::make_unique<Impl>(device_memory_)} {}
|
||||
|
||||
ShaderCache::~ShaderCache() = default;
|
||||
|
||||
void ShaderCache::InvalidateRegion(VAddr addr, size_t size) {
|
||||
impl->InvalidateRegion(addr, size);
|
||||
}
|
||||
|
||||
const ShaderInfo* ShaderCache::MakeShaderInfo(GenericEnvironment& env, VAddr cpu_addr) {
|
||||
auto info = std::make_unique<ShaderInfo>();
|
||||
if (const std::optional<u64> cached_hash{env.Analyze()}) {
|
||||
info->unique_hash = *cached_hash;
|
||||
info->size_bytes = env.CachedSizeBytes();
|
||||
} else {
|
||||
// Slow path, not really hit on commercial games
|
||||
// Build a control flow graph to get the real shader size
|
||||
Shader::ObjectPool<Shader::Maxwell::Flow::Block> flow_block;
|
||||
Shader::Maxwell::Flow::CFG cfg{env, flow_block, env.StartAddress()};
|
||||
info->unique_hash = env.CalculateHash();
|
||||
info->size_bytes = env.ReadSizeBytes();
|
||||
}
|
||||
const size_t size_bytes{info->size_bytes};
|
||||
const ShaderInfo* const result{info.get()};
|
||||
Register(std::move(info), cpu_addr, size_bytes);
|
||||
return result;
|
||||
void ShaderCache::OnCacheInvalidation(VAddr addr, size_t size) {
|
||||
impl->OnCacheInvalidation(addr, size);
|
||||
}
|
||||
|
||||
void ShaderCache::SyncGuestHost() {
|
||||
impl->SyncGuestHost();
|
||||
}
|
||||
|
||||
bool ShaderCache::RefreshStages(std::array<u64, 6>& unique_hashes) {
|
||||
return impl->RefreshStages(unique_hashes);
|
||||
}
|
||||
|
||||
const ShaderInfo* ShaderCache::ComputeShader() {
|
||||
return impl->ComputeShader();
|
||||
}
|
||||
|
||||
void ShaderCache::GetGraphicsEnvironments(GraphicsEnvironments& result,
|
||||
const std::array<u64, NUM_PROGRAMS>& unique_hashes) {
|
||||
impl->GetGraphicsEnvironments(result, unique_hashes);
|
||||
}
|
||||
|
||||
ShaderInfo* ShaderCache::TryGet(VAddr addr) const {
|
||||
return impl->TryGet(addr);
|
||||
}
|
||||
|
||||
void ShaderCache::Register(std::unique_ptr<ShaderInfo> data, VAddr addr, size_t size) {
|
||||
impl->Register(std::move(data), addr, size);
|
||||
}
|
||||
|
||||
} // namespace VideoCommon
|
||||
|
|
|
|||
Loading…
Reference in a new issue