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https://git.suyu.dev/suyu/suyu.git
synced 2024-11-10 00:42:45 +01:00
shader: Reimplement GetCbufU64 as GetCbufU32x2
It may generate better code on some compilers and it's easier to handle.
This commit is contained in:
parent
5b3c6d59c2
commit
3f594dd86b
9 changed files with 21 additions and 22 deletions
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@ -308,8 +308,8 @@ void EmitContext::DefineConstantBuffers(const Info& info, u32& binding) {
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if (True(info.used_constant_buffer_types & IR::Type::F32)) {
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DefineConstantBuffers(info, &UniformDefinitions::F32, binding, F32[1], 'f', sizeof(f32));
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}
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if (True(info.used_constant_buffer_types & IR::Type::U64)) {
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DefineConstantBuffers(info, &UniformDefinitions::U64, binding, U64, 'u', sizeof(u64));
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if (True(info.used_constant_buffer_types & IR::Type::U32x2)) {
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DefineConstantBuffers(info, &UniformDefinitions::U32x2, binding, U32[2], 'u', sizeof(u64));
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}
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for (const ConstantBufferDescriptor& desc : info.constant_buffer_descriptors) {
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binding += desc.count;
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@ -42,7 +42,7 @@ struct UniformDefinitions {
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Id S16{};
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Id U32{};
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Id F32{};
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Id U64{};
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Id U32x2{};
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};
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class EmitContext final : public Sirit::Module {
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@ -47,7 +47,7 @@ Id EmitGetCbufU16(EmitContext& ctx, const IR::Value& binding, const IR::Value& o
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Id EmitGetCbufS16(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufU64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetCbufU32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr);
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value);
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void EmitGetAttributeIndexed(EmitContext& ctx);
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@ -153,8 +153,8 @@ Id EmitGetCbufF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& o
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return GetCbuf(ctx, ctx.F32[1], &UniformDefinitions::F32, sizeof(f32), binding, offset);
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}
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Id EmitGetCbufU64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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return GetCbuf(ctx, ctx.U64, &UniformDefinitions::U64, sizeof(u64), binding, offset);
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Id EmitGetCbufU32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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return GetCbuf(ctx, ctx.U32[2], &UniformDefinitions::U32x2, sizeof(u32[2]), binding, offset);
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}
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr) {
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@ -162,8 +162,8 @@ U32 IREmitter::GetCbuf(const U32& binding, const U32& byte_offset) {
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return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
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}
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UAny IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
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bool is_signed) {
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Value IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
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bool is_signed) {
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switch (bitsize) {
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case 8:
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return Inst<U32>(is_signed ? Opcode::GetCbufS8 : Opcode::GetCbufU8, binding, byte_offset);
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@ -172,7 +172,7 @@ UAny IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsi
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case 32:
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return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
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case 64:
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return Inst<U64>(Opcode::GetCbufU64, binding, byte_offset);
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return Inst(Opcode::GetCbufU32x2, binding, byte_offset);
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default:
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throw InvalidArgument("Invalid bit size {}", bitsize);
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}
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@ -56,8 +56,8 @@ public:
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void SetIndirectBranchVariable(const U32& value);
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[[nodiscard]] U32 GetCbuf(const U32& binding, const U32& byte_offset);
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[[nodiscard]] UAny GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
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bool is_signed);
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[[nodiscard]] Value GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
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bool is_signed);
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[[nodiscard]] F32 GetFloatCbuf(const U32& binding, const U32& byte_offset);
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[[nodiscard]] U1 GetZFlag();
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@ -40,7 +40,7 @@ OPCODE(GetCbufU16, U32, U32,
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OPCODE(GetCbufS16, U32, U32, U32, )
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OPCODE(GetCbufU32, U32, U32, U32, )
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OPCODE(GetCbufF32, F32, U32, U32, )
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OPCODE(GetCbufU64, U64, U32, U32, )
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OPCODE(GetCbufU32x2, U32x2, U32, U32, )
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OPCODE(GetAttribute, F32, Attribute, )
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OPCODE(SetAttribute, Void, Attribute, F32, )
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OPCODE(GetAttributeIndexed, F32, U32, )
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@ -30,25 +30,25 @@ void TranslatorVisitor::LDC(u64 insn) {
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const auto [index, offset]{Slot(ir, ldc.mode, imm_index, reg, imm)};
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switch (ldc.size) {
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case Size::U8:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, false));
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 8, false)});
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break;
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case Size::S8:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, true));
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 8, true)});
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break;
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case Size::U16:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, false));
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 16, false)});
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break;
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case Size::S16:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, true));
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 16, true)});
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break;
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case Size::B32:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 32, false));
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 32, false)});
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break;
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case Size::B64: {
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if (!IR::IsAligned(ldc.dest_reg, 2)) {
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throw NotImplementedException("Unaligned destination register");
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}
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const IR::Value vector{ir.UnpackUint2x32(ir.GetCbuf(index, offset, 64, false))};
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const IR::Value vector{ir.GetCbuf(index, offset, 64, false)};
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for (int i = 0; i < 2; ++i) {
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X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
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}
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@ -271,7 +271,6 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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break;
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}
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switch (inst.Opcode()) {
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case IR::Opcode::GetCbufU64:
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case IR::Opcode::UndefU64:
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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@ -349,7 +348,7 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::GetCbufS16:
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case IR::Opcode::GetCbufU32:
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case IR::Opcode::GetCbufF32:
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case IR::Opcode::GetCbufU64: {
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case IR::Opcode::GetCbufU32x2: {
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if (const IR::Value index{inst.Arg(0)}; index.IsImmediate()) {
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AddConstantBufferDescriptor(info, index.U32(), 1);
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} else {
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@ -370,8 +369,8 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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case IR::Opcode::GetCbufF32:
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info.used_constant_buffer_types |= IR::Type::F32;
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break;
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case IR::Opcode::GetCbufU64:
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info.used_constant_buffer_types |= IR::Type::U64;
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case IR::Opcode::GetCbufU32x2:
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info.used_constant_buffer_types |= IR::Type::U32x2;
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break;
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default:
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break;
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