N-archive/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-27 09:12:46 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

shader: Implement SR_LaneId

Browse source
This commit is contained in:
FernandoS27 2021-04-02 23:05:47 +02:00 committed by ameerj
parent 595806fb1c
commit 45d547af11
7 changed files with 15 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/shader_recompiler/backend/spirv/emit_spirv.h
View file

@ -71,6 +71,7 @@ void EmitSetMXFlag(EmitContext& ctx);
Id EmitWorkgroupId(EmitContext& ctx);
Id EmitLocalInvocationId(EmitContext& ctx);
Id EmitLoadLocal(EmitContext& ctx, Id word_offset);
Id EmitLaneId(EmitContext& ctx);
void EmitWriteLocal(EmitContext& ctx, Id word_offset, Id value);
Id EmitUndefU1(EmitContext& ctx);
Id EmitUndefU8(EmitContext& ctx);

4
src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
View file

@ -303,6 +303,10 @@ Id EmitLocalInvocationId(EmitContext& ctx) {
return ctx.OpLoad(ctx.U32[3], ctx.local_invocation_id);
}
Id EmitLaneId(EmitContext& ctx) {
return ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id);
}
Id EmitLoadLocal(EmitContext& ctx, Id word_offset) {
const Id pointer{ctx.OpAccessChain(ctx.private_u32, ctx.local_memory, word_offset)};
return ctx.OpLoad(ctx.U32[1], pointer);

4
src/shader_recompiler/frontend/ir/ir_emitter.cpp
View file

@ -355,6 +355,10 @@ U32 IREmitter::LocalInvocationIdZ() {
return U32{CompositeExtract(Inst(Opcode::LocalInvocationId), 2)};
}
U32 IREmitter::LaneId() {
return Inst<U32>(Opcode::LaneId);
}
U32 IREmitter::LoadGlobalU8(const U64& address) {
return Inst<U32>(Opcode::LoadGlobalU8, address);
}

2
src/shader_recompiler/frontend/ir/ir_emitter.h
View file

@ -97,6 +97,8 @@ public:
[[nodiscard]] U32 LocalInvocationIdY();
[[nodiscard]] U32 LocalInvocationIdZ();
[[nodiscard]] U32 LaneId();
[[nodiscard]] U32 LoadGlobalU8(const U64& address);
[[nodiscard]] U32 LoadGlobalS8(const U64& address);
[[nodiscard]] U32 LoadGlobalU16(const U64& address);

1
src/shader_recompiler/frontend/ir/opcodes.inc
View file

@ -63,6 +63,7 @@ OPCODE(SetTRFlag, Void, U1,
OPCODE(SetMXFlag, Void, U1, )
OPCODE(WorkgroupId, U32x3, )
OPCODE(LocalInvocationId, U32x3, )
OPCODE(LaneId, U32, )
// Undefined
OPCODE(UndefU1, U1, )

2
src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
View file

@ -99,6 +99,8 @@ enum class SpecialRegister : u64 {
return ir.Imm32(Common::BitCast<u32>(1.0f));
case SpecialRegister::SR_WSCALEFACTOR_Z:
return ir.Imm32(Common::BitCast<u32>(1.0f));
case SpecialRegister::SR_LANEID:
return ir.LaneId();
default:
throw NotImplementedException("S2R special register {}", special_register);
}

1
src/shader_recompiler/ir_opt/collect_shader_info_pass.cpp
View file

@ -340,6 +340,7 @@ void VisitUsages(Info& info, IR::Inst& inst) {
case IR::Opcode::ShuffleUp:
case IR::Opcode::ShuffleDown:
case IR::Opcode::ShuffleButterfly:
case IR::Opcode::LaneId:
info.uses_subgroup_invocation_id = true;
break;
case IR::Opcode::GetCbufU8: