mirror of
https://git.suyu.dev/suyu/suyu.git
synced 2024-12-23 00:40:58 +01:00
video_core: Silent miscellaneous warnings (#2820)
* texture_cache/surface_params: Remove unused local variable * rasterizer_interface: Add missing documentation commentary * maxwell_dma: Remove unused rasterizer reference * video_core/gpu: Sort member declaration order to silent -Wreorder warning * fermi_2d: Remove unused MemoryManager reference * video_core: Silent unused variable warnings * buffer_cache: Silent -Wreorder warnings * kepler_memory: Remove unused MemoryManager reference * gl_texture_cache: Add missing override * buffer_cache: Add missing include * shader/decode: Remove unused variables
This commit is contained in:
parent
67cc2d5046
commit
4d4f9cc104
23 changed files with 22 additions and 48 deletions
|
@ -69,7 +69,6 @@ protected:
|
||||||
private:
|
private:
|
||||||
CacheAddr cache_addr{};
|
CacheAddr cache_addr{};
|
||||||
CacheAddr cache_addr_end{};
|
CacheAddr cache_addr_end{};
|
||||||
u64 pages{};
|
|
||||||
std::size_t size{};
|
std::size_t size{};
|
||||||
u64 epoch{};
|
u64 epoch{};
|
||||||
};
|
};
|
||||||
|
|
|
@ -18,10 +18,7 @@
|
||||||
#include "video_core/buffer_cache/buffer_block.h"
|
#include "video_core/buffer_cache/buffer_block.h"
|
||||||
#include "video_core/buffer_cache/map_interval.h"
|
#include "video_core/buffer_cache/map_interval.h"
|
||||||
#include "video_core/memory_manager.h"
|
#include "video_core/memory_manager.h"
|
||||||
|
#include "video_core/rasterizer_interface.h"
|
||||||
namespace VideoCore {
|
|
||||||
class RasterizerInterface;
|
|
||||||
}
|
|
||||||
|
|
||||||
namespace VideoCommon {
|
namespace VideoCommon {
|
||||||
|
|
||||||
|
@ -348,7 +345,6 @@ private:
|
||||||
const CacheAddr cache_addr_end = cache_addr + size - 1;
|
const CacheAddr cache_addr_end = cache_addr + size - 1;
|
||||||
u64 page_start = cache_addr >> block_page_bits;
|
u64 page_start = cache_addr >> block_page_bits;
|
||||||
const u64 page_end = cache_addr_end >> block_page_bits;
|
const u64 page_end = cache_addr_end >> block_page_bits;
|
||||||
const u64 num_pages = page_end - page_start + 1;
|
|
||||||
while (page_start <= page_end) {
|
while (page_start <= page_end) {
|
||||||
auto it = blocks.find(page_start);
|
auto it = blocks.find(page_start);
|
||||||
if (it == blocks.end()) {
|
if (it == blocks.end()) {
|
||||||
|
@ -417,7 +413,10 @@ private:
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
VideoCore::RasterizerInterface& rasterizer;
|
||||||
|
Core::System& system;
|
||||||
std::unique_ptr<StreamBuffer> stream_buffer;
|
std::unique_ptr<StreamBuffer> stream_buffer;
|
||||||
|
|
||||||
TBufferType stream_buffer_handle{};
|
TBufferType stream_buffer_handle{};
|
||||||
|
|
||||||
bool invalidated = false;
|
bool invalidated = false;
|
||||||
|
@ -441,8 +440,7 @@ private:
|
||||||
std::list<TBuffer> pending_destruction{};
|
std::list<TBuffer> pending_destruction{};
|
||||||
u64 epoch{};
|
u64 epoch{};
|
||||||
u64 modified_ticks{};
|
u64 modified_ticks{};
|
||||||
VideoCore::RasterizerInterface& rasterizer;
|
|
||||||
Core::System& system;
|
|
||||||
std::recursive_mutex mutex;
|
std::recursive_mutex mutex;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -10,8 +10,7 @@
|
||||||
|
|
||||||
namespace Tegra::Engines {
|
namespace Tegra::Engines {
|
||||||
|
|
||||||
Fermi2D::Fermi2D(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
|
Fermi2D::Fermi2D(VideoCore::RasterizerInterface& rasterizer) : rasterizer{rasterizer} {}
|
||||||
: rasterizer{rasterizer}, memory_manager{memory_manager} {}
|
|
||||||
|
|
||||||
void Fermi2D::CallMethod(const GPU::MethodCall& method_call) {
|
void Fermi2D::CallMethod(const GPU::MethodCall& method_call) {
|
||||||
ASSERT_MSG(method_call.method < Regs::NUM_REGS,
|
ASSERT_MSG(method_call.method < Regs::NUM_REGS,
|
||||||
|
|
|
@ -33,7 +33,7 @@ namespace Tegra::Engines {
|
||||||
|
|
||||||
class Fermi2D final {
|
class Fermi2D final {
|
||||||
public:
|
public:
|
||||||
explicit Fermi2D(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager);
|
explicit Fermi2D(VideoCore::RasterizerInterface& rasterizer);
|
||||||
~Fermi2D() = default;
|
~Fermi2D() = default;
|
||||||
|
|
||||||
/// Write the value to the register identified by method.
|
/// Write the value to the register identified by method.
|
||||||
|
@ -145,7 +145,6 @@ public:
|
||||||
|
|
||||||
private:
|
private:
|
||||||
VideoCore::RasterizerInterface& rasterizer;
|
VideoCore::RasterizerInterface& rasterizer;
|
||||||
MemoryManager& memory_manager;
|
|
||||||
|
|
||||||
/// Performs the copy from the source surface to the destination surface as configured in the
|
/// Performs the copy from the source surface to the destination surface as configured in the
|
||||||
/// registers.
|
/// registers.
|
||||||
|
|
|
@ -15,7 +15,7 @@
|
||||||
namespace Tegra::Engines {
|
namespace Tegra::Engines {
|
||||||
|
|
||||||
KeplerMemory::KeplerMemory(Core::System& system, MemoryManager& memory_manager)
|
KeplerMemory::KeplerMemory(Core::System& system, MemoryManager& memory_manager)
|
||||||
: system{system}, memory_manager{memory_manager}, upload_state{memory_manager, regs.upload} {}
|
: system{system}, upload_state{memory_manager, regs.upload} {}
|
||||||
|
|
||||||
KeplerMemory::~KeplerMemory() = default;
|
KeplerMemory::~KeplerMemory() = default;
|
||||||
|
|
||||||
|
|
|
@ -65,7 +65,6 @@ public:
|
||||||
|
|
||||||
private:
|
private:
|
||||||
Core::System& system;
|
Core::System& system;
|
||||||
MemoryManager& memory_manager;
|
|
||||||
Upload::State upload_state;
|
Upload::State upload_state;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -524,7 +524,7 @@ void Maxwell3D::ProcessQueryCondition() {
|
||||||
void Maxwell3D::ProcessSyncPoint() {
|
void Maxwell3D::ProcessSyncPoint() {
|
||||||
const u32 sync_point = regs.sync_info.sync_point.Value();
|
const u32 sync_point = regs.sync_info.sync_point.Value();
|
||||||
const u32 increment = regs.sync_info.increment.Value();
|
const u32 increment = regs.sync_info.increment.Value();
|
||||||
const u32 cache_flush = regs.sync_info.unknown.Value();
|
[[maybe_unused]] const u32 cache_flush = regs.sync_info.unknown.Value();
|
||||||
if (increment) {
|
if (increment) {
|
||||||
system.GPU().IncrementSyncPoint(sync_point);
|
system.GPU().IncrementSyncPoint(sync_point);
|
||||||
}
|
}
|
||||||
|
@ -626,10 +626,10 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
|
||||||
Texture::TICEntry tic_entry;
|
Texture::TICEntry tic_entry;
|
||||||
memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry));
|
memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry));
|
||||||
|
|
||||||
const auto r_type{tic_entry.r_type.Value()};
|
[[maybe_unused]] const auto r_type{tic_entry.r_type.Value()};
|
||||||
const auto g_type{tic_entry.g_type.Value()};
|
[[maybe_unused]] const auto g_type{tic_entry.g_type.Value()};
|
||||||
const auto b_type{tic_entry.b_type.Value()};
|
[[maybe_unused]] const auto b_type{tic_entry.b_type.Value()};
|
||||||
const auto a_type{tic_entry.a_type.Value()};
|
[[maybe_unused]] const auto a_type{tic_entry.a_type.Value()};
|
||||||
|
|
||||||
// TODO(Subv): Different data types for separate components are not supported
|
// TODO(Subv): Different data types for separate components are not supported
|
||||||
DEBUG_ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
|
DEBUG_ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
|
||||||
|
|
|
@ -8,15 +8,13 @@
|
||||||
#include "video_core/engines/maxwell_3d.h"
|
#include "video_core/engines/maxwell_3d.h"
|
||||||
#include "video_core/engines/maxwell_dma.h"
|
#include "video_core/engines/maxwell_dma.h"
|
||||||
#include "video_core/memory_manager.h"
|
#include "video_core/memory_manager.h"
|
||||||
#include "video_core/rasterizer_interface.h"
|
|
||||||
#include "video_core/renderer_base.h"
|
#include "video_core/renderer_base.h"
|
||||||
#include "video_core/textures/decoders.h"
|
#include "video_core/textures/decoders.h"
|
||||||
|
|
||||||
namespace Tegra::Engines {
|
namespace Tegra::Engines {
|
||||||
|
|
||||||
MaxwellDMA::MaxwellDMA(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
|
MaxwellDMA::MaxwellDMA(Core::System& system, MemoryManager& memory_manager)
|
||||||
MemoryManager& memory_manager)
|
: system{system}, memory_manager{memory_manager} {}
|
||||||
: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager} {}
|
|
||||||
|
|
||||||
void MaxwellDMA::CallMethod(const GPU::MethodCall& method_call) {
|
void MaxwellDMA::CallMethod(const GPU::MethodCall& method_call) {
|
||||||
ASSERT_MSG(method_call.method < Regs::NUM_REGS,
|
ASSERT_MSG(method_call.method < Regs::NUM_REGS,
|
||||||
|
|
|
@ -20,10 +20,6 @@ namespace Tegra {
|
||||||
class MemoryManager;
|
class MemoryManager;
|
||||||
}
|
}
|
||||||
|
|
||||||
namespace VideoCore {
|
|
||||||
class RasterizerInterface;
|
|
||||||
}
|
|
||||||
|
|
||||||
namespace Tegra::Engines {
|
namespace Tegra::Engines {
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -33,8 +29,7 @@ namespace Tegra::Engines {
|
||||||
|
|
||||||
class MaxwellDMA final {
|
class MaxwellDMA final {
|
||||||
public:
|
public:
|
||||||
explicit MaxwellDMA(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
|
explicit MaxwellDMA(Core::System& system, MemoryManager& memory_manager);
|
||||||
MemoryManager& memory_manager);
|
|
||||||
~MaxwellDMA() = default;
|
~MaxwellDMA() = default;
|
||||||
|
|
||||||
/// Write the value to the register identified by method.
|
/// Write the value to the register identified by method.
|
||||||
|
@ -180,8 +175,6 @@ public:
|
||||||
private:
|
private:
|
||||||
Core::System& system;
|
Core::System& system;
|
||||||
|
|
||||||
VideoCore::RasterizerInterface& rasterizer;
|
|
||||||
|
|
||||||
MemoryManager& memory_manager;
|
MemoryManager& memory_manager;
|
||||||
|
|
||||||
std::vector<u8> read_buffer;
|
std::vector<u8> read_buffer;
|
||||||
|
|
|
@ -35,9 +35,9 @@ GPU::GPU(Core::System& system, VideoCore::RendererBase& renderer, bool is_async)
|
||||||
memory_manager = std::make_unique<Tegra::MemoryManager>(system, rasterizer);
|
memory_manager = std::make_unique<Tegra::MemoryManager>(system, rasterizer);
|
||||||
dma_pusher = std::make_unique<Tegra::DmaPusher>(*this);
|
dma_pusher = std::make_unique<Tegra::DmaPusher>(*this);
|
||||||
maxwell_3d = std::make_unique<Engines::Maxwell3D>(system, rasterizer, *memory_manager);
|
maxwell_3d = std::make_unique<Engines::Maxwell3D>(system, rasterizer, *memory_manager);
|
||||||
fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer, *memory_manager);
|
fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer);
|
||||||
kepler_compute = std::make_unique<Engines::KeplerCompute>(system, rasterizer, *memory_manager);
|
kepler_compute = std::make_unique<Engines::KeplerCompute>(system, rasterizer, *memory_manager);
|
||||||
maxwell_dma = std::make_unique<Engines::MaxwellDMA>(system, rasterizer, *memory_manager);
|
maxwell_dma = std::make_unique<Engines::MaxwellDMA>(system, *memory_manager);
|
||||||
kepler_memory = std::make_unique<Engines::KeplerMemory>(system, *memory_manager);
|
kepler_memory = std::make_unique<Engines::KeplerMemory>(system, *memory_manager);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -285,8 +285,8 @@ private:
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
std::unique_ptr<Tegra::DmaPusher> dma_pusher;
|
std::unique_ptr<Tegra::DmaPusher> dma_pusher;
|
||||||
VideoCore::RendererBase& renderer;
|
|
||||||
Core::System& system;
|
Core::System& system;
|
||||||
|
VideoCore::RendererBase& renderer;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
std::unique_ptr<Tegra::MemoryManager> memory_manager;
|
std::unique_ptr<Tegra::MemoryManager> memory_manager;
|
||||||
|
|
|
@ -50,7 +50,7 @@ public:
|
||||||
/// and invalidated
|
/// and invalidated
|
||||||
virtual void FlushAndInvalidateRegion(CacheAddr addr, u64 size) = 0;
|
virtual void FlushAndInvalidateRegion(CacheAddr addr, u64 size) = 0;
|
||||||
|
|
||||||
// Notify the rasterizer to send all written commands to the host GPU.
|
/// Notify the rasterizer to send all written commands to the host GPU.
|
||||||
virtual void FlushCommands() = 0;
|
virtual void FlushCommands() = 0;
|
||||||
|
|
||||||
/// Notify rasterizer that a frame is about to finish
|
/// Notify rasterizer that a frame is about to finish
|
||||||
|
|
|
@ -708,8 +708,6 @@ void RasterizerOpenGL::DrawArrays() {
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
const auto& regs = gpu.regs;
|
|
||||||
|
|
||||||
SyncColorMask();
|
SyncColorMask();
|
||||||
SyncFragmentColorClampState();
|
SyncFragmentColorClampState();
|
||||||
SyncMultiSampleState();
|
SyncMultiSampleState();
|
||||||
|
|
|
@ -295,7 +295,7 @@ std::set<GLenum> GetSupportedFormats() {
|
||||||
|
|
||||||
CachedShader::CachedShader(const ShaderParameters& params, ProgramType program_type,
|
CachedShader::CachedShader(const ShaderParameters& params, ProgramType program_type,
|
||||||
GLShader::ProgramResult result)
|
GLShader::ProgramResult result)
|
||||||
: RasterizerCacheObject{params.host_ptr}, host_ptr{params.host_ptr}, cpu_addr{params.cpu_addr},
|
: RasterizerCacheObject{params.host_ptr}, cpu_addr{params.cpu_addr},
|
||||||
unique_identifier{params.unique_identifier}, program_type{program_type},
|
unique_identifier{params.unique_identifier}, program_type{program_type},
|
||||||
disk_cache{params.disk_cache}, precompiled_programs{params.precompiled_programs},
|
disk_cache{params.disk_cache}, precompiled_programs{params.precompiled_programs},
|
||||||
entries{result.second}, code{std::move(result.first)}, shader_length{entries.shader_length} {}
|
entries{result.second}, code{std::move(result.first)}, shader_length{entries.shader_length} {}
|
||||||
|
|
|
@ -106,7 +106,6 @@ private:
|
||||||
|
|
||||||
ShaderDiskCacheUsage GetUsage(const ProgramVariant& variant) const;
|
ShaderDiskCacheUsage GetUsage(const ProgramVariant& variant) const;
|
||||||
|
|
||||||
u8* host_ptr{};
|
|
||||||
VAddr cpu_addr{};
|
VAddr cpu_addr{};
|
||||||
u64 unique_identifier{};
|
u64 unique_identifier{};
|
||||||
ProgramType program_type{};
|
ProgramType program_type{};
|
||||||
|
|
|
@ -51,7 +51,7 @@ public:
|
||||||
}
|
}
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
void DecorateSurfaceName();
|
void DecorateSurfaceName() override;
|
||||||
|
|
||||||
View CreateView(const ViewParams& view_key) override;
|
View CreateView(const ViewParams& view_key) override;
|
||||||
View CreateViewInner(const ViewParams& view_key, bool is_proxy);
|
View CreateViewInner(const ViewParams& view_key, bool is_proxy);
|
||||||
|
|
|
@ -15,7 +15,6 @@ using Tegra::Shader::OpCode;
|
||||||
|
|
||||||
u32 ShaderIR::DecodeFloatSet(NodeBlock& bb, u32 pc) {
|
u32 ShaderIR::DecodeFloatSet(NodeBlock& bb, u32 pc) {
|
||||||
const Instruction instr = {program_code[pc]};
|
const Instruction instr = {program_code[pc]};
|
||||||
const auto opcode = OpCode::Decode(instr);
|
|
||||||
|
|
||||||
const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fset.abs_a != 0,
|
const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fset.abs_a != 0,
|
||||||
instr.fset.neg_a != 0);
|
instr.fset.neg_a != 0);
|
||||||
|
|
|
@ -16,7 +16,6 @@ using Tegra::Shader::Pred;
|
||||||
|
|
||||||
u32 ShaderIR::DecodeFloatSetPredicate(NodeBlock& bb, u32 pc) {
|
u32 ShaderIR::DecodeFloatSetPredicate(NodeBlock& bb, u32 pc) {
|
||||||
const Instruction instr = {program_code[pc]};
|
const Instruction instr = {program_code[pc]};
|
||||||
const auto opcode = OpCode::Decode(instr);
|
|
||||||
|
|
||||||
const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fsetp.abs_a != 0,
|
const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fsetp.abs_a != 0,
|
||||||
instr.fsetp.neg_a != 0);
|
instr.fsetp.neg_a != 0);
|
||||||
|
|
|
@ -14,7 +14,6 @@ using Tegra::Shader::OpCode;
|
||||||
|
|
||||||
u32 ShaderIR::DecodeIntegerSet(NodeBlock& bb, u32 pc) {
|
u32 ShaderIR::DecodeIntegerSet(NodeBlock& bb, u32 pc) {
|
||||||
const Instruction instr = {program_code[pc]};
|
const Instruction instr = {program_code[pc]};
|
||||||
const auto opcode = OpCode::Decode(instr);
|
|
||||||
|
|
||||||
const Node op_a = GetRegister(instr.gpr8);
|
const Node op_a = GetRegister(instr.gpr8);
|
||||||
const Node op_b = [&]() {
|
const Node op_b = [&]() {
|
||||||
|
|
|
@ -16,7 +16,6 @@ using Tegra::Shader::Pred;
|
||||||
|
|
||||||
u32 ShaderIR::DecodeIntegerSetPredicate(NodeBlock& bb, u32 pc) {
|
u32 ShaderIR::DecodeIntegerSetPredicate(NodeBlock& bb, u32 pc) {
|
||||||
const Instruction instr = {program_code[pc]};
|
const Instruction instr = {program_code[pc]};
|
||||||
const auto opcode = OpCode::Decode(instr);
|
|
||||||
|
|
||||||
const Node op_a = GetRegister(instr.gpr8);
|
const Node op_a = GetRegister(instr.gpr8);
|
||||||
|
|
||||||
|
|
|
@ -15,7 +15,6 @@ using Tegra::Shader::OpCode;
|
||||||
|
|
||||||
u32 ShaderIR::DecodePredicateSetRegister(NodeBlock& bb, u32 pc) {
|
u32 ShaderIR::DecodePredicateSetRegister(NodeBlock& bb, u32 pc) {
|
||||||
const Instruction instr = {program_code[pc]};
|
const Instruction instr = {program_code[pc]};
|
||||||
const auto opcode = OpCode::Decode(instr);
|
|
||||||
|
|
||||||
UNIMPLEMENTED_IF_MSG(instr.generates_cc,
|
UNIMPLEMENTED_IF_MSG(instr.generates_cc,
|
||||||
"Condition codes generation in PSET is not implemented");
|
"Condition codes generation in PSET is not implemented");
|
||||||
|
|
|
@ -58,7 +58,6 @@ public:
|
||||||
std::size_t GetHostSizeInBytes() const {
|
std::size_t GetHostSizeInBytes() const {
|
||||||
std::size_t host_size_in_bytes;
|
std::size_t host_size_in_bytes;
|
||||||
if (GetCompressionType() == SurfaceCompression::Converted) {
|
if (GetCompressionType() == SurfaceCompression::Converted) {
|
||||||
constexpr std::size_t rgb8_bpp = 4ULL;
|
|
||||||
// ASTC is uncompressed in software, in emulated as RGBA8
|
// ASTC is uncompressed in software, in emulated as RGBA8
|
||||||
host_size_in_bytes = 0;
|
host_size_in_bytes = 0;
|
||||||
for (u32 level = 0; level < num_levels; ++level) {
|
for (u32 level = 0; level < num_levels; ++level) {
|
||||||
|
|
|
@ -308,8 +308,6 @@ protected:
|
||||||
if (!guard_render_targets && surface->IsRenderTarget()) {
|
if (!guard_render_targets && surface->IsRenderTarget()) {
|
||||||
ManageRenderTargetUnregister(surface);
|
ManageRenderTargetUnregister(surface);
|
||||||
}
|
}
|
||||||
const GPUVAddr gpu_addr = surface->GetGpuAddr();
|
|
||||||
const CacheAddr cache_ptr = surface->GetCacheAddr();
|
|
||||||
const std::size_t size = surface->GetSizeInBytes();
|
const std::size_t size = surface->GetSizeInBytes();
|
||||||
const VAddr cpu_addr = surface->GetCpuAddr();
|
const VAddr cpu_addr = surface->GetCpuAddr();
|
||||||
rasterizer.UpdatePagesCachedCount(cpu_addr, size, -1);
|
rasterizer.UpdatePagesCachedCount(cpu_addr, size, -1);
|
||||||
|
|
Loading…
Reference in a new issue