Merge pull request #1106 from Subv/multiple_rendertargets

Shaders: Write all the enabled color outputs when a fragment shader exits.

src/video_core/renderer_opengl/gl_shader_decompiler.cpp

@@ -26,6 +26,7 @@ using Tegra::Shader::Sampler;
 using Tegra::Shader::SubOp;
 
 constexpr u32 PROGRAM_END = MAX_PROGRAM_CODE_LENGTH;
+constexpr u32 PROGRAM_HEADER_SIZE = 0x50;
 
 class DecompileFail : public std::runtime_error {
 public:
@@ -621,6 +622,23 @@ public:
     }
 
 private:
+    // Shader program header for a Fragment Shader.
+    struct FragmentHeader {
+        INSERT_PADDING_WORDS(5);
+        INSERT_PADDING_WORDS(13);
+        u32 enabled_color_outputs;
+        union {
+            BitField<0, 1, u32> writes_samplemask;
+            BitField<1, 1, u32> writes_depth;
+        };
+
+        bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
+            u32 bit = render_target * 4 + component;
+            return enabled_color_outputs & (1 << bit);
+        }
+    };
+    static_assert(sizeof(FragmentHeader) == PROGRAM_HEADER_SIZE, "FragmentHeader size is wrong");
+
     /// Gets the Subroutine object corresponding to the specified address.
     const Subroutine& GetSubroutine(u32 begin, u32 end) const {
         auto iter = subroutines.find(Subroutine{begin, end, suffix});
@@ -894,6 +912,31 @@ private:
         shader.AddLine('}');
     }
 
+    /// Writes the output values from a fragment shader to the corresponding GLSL output variables.
+    void EmitFragmentOutputsWrite() {
+        ASSERT(stage == Maxwell3D::Regs::ShaderStage::Fragment);
+        FragmentHeader header;
+        std::memcpy(&header, program_code.data(), PROGRAM_HEADER_SIZE);
+
+        ASSERT_MSG(header.writes_depth == 0, "Depth write is unimplemented");
+        ASSERT_MSG(header.writes_samplemask == 0, "Samplemask write is unimplemented");
+
+        // Write the color outputs using the data in the shader registers, disabled
+        // rendertargets/components are skipped in the register assignment.
+        u32 current_reg = 0;
+        for (u32 render_target = 0; render_target < Maxwell3D::Regs::NumRenderTargets;
+             ++render_target) {
+            // TODO(Subv): Figure out how dual-source blending is configured in the Switch.
+            for (u32 component = 0; component < 4; ++component) {
+                if (header.IsColorComponentOutputEnabled(render_target, component)) {
+                    shader.AddLine(fmt::format("color[{}][{}] = {};", render_target, component,
+                                               regs.GetRegisterAsFloat(current_reg)));
+                    ++current_reg;
+                }
+            }
+        }
+    }
+
     /**
      * Compiles a single instruction from Tegra to GLSL.
      * @param offset the offset of the Tegra shader instruction.
@@ -1969,12 +2012,8 @@ private:
         default: {
             switch (opcode->GetId()) {
             case OpCode::Id::EXIT: {
-                // Final color output is currently hardcoded to GPR0-3 for fragment shaders
                 if (stage == Maxwell3D::Regs::ShaderStage::Fragment) {
-                    shader.AddLine("color.r = " + regs.GetRegisterAsFloat(0) + ';');
+                    EmitFragmentOutputsWrite();
-                    shader.AddLine("color.g = " + regs.GetRegisterAsFloat(1) + ';');
-                    shader.AddLine("color.b = " + regs.GetRegisterAsFloat(2) + ';');
-                    shader.AddLine("color.a = " + regs.GetRegisterAsFloat(3) + ';');
                 }
 
                 switch (instr.flow.cond) {

src/video_core/renderer_opengl/gl_shader_gen.cpp

@@ -87,7 +87,7 @@ ProgramResult GenerateFragmentShader(const ShaderSetup& setup, const MaxwellFSCo
             .get_value_or({});
     out += R"(
 in vec4 position;
-out vec4 color;
+layout(location = 0) out vec4 color[8];
 
 layout (std140) uniform fs_config {
     vec4 viewport_flip;