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Merge pull request #8098 from merryhime/ic-ivau

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dynarmic: Invalidate CPU cache on all cores
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bunnei 2022-03-28 15:45:52 -07:00 committed by GitHub
commit 642913b0d1
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2 changed files with 5 additions and 3 deletions
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2
externals/dynarmic vendored

@ -1 +1 @@
Subproject commit e1a266b9299be81cc0318c7e25b00388c342704f Subproject commit af2d50288fc537201014c4230bb55ab9018a7438

6
src/core/arm/dynarmic/arm_dynarmic_64.cpp
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@ -93,17 +93,19 @@ public:
static constexpr u64 ICACHE_LINE_SIZE = 64; static constexpr u64 ICACHE_LINE_SIZE = 64;
const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1); const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE); parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
break; break;
} }
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU: case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
parent.ClearInstructionCache(); parent.system.InvalidateCpuInstructionCaches();
break; break;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable: case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default: default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op); LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
break; break;
} }
parent.jit->HaltExecution();
} }
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override { void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {