N-archive/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-12-24 17:30:56 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

dyncom: Handle the ARM A2 encoding of STRT/LDRT

Browse source 
These were also missing the shifted register case.
This commit is contained in:
Lioncash 2015-01-17 13:51:00 -05:00
parent 14308a88a7
commit 8575010a68
1 changed files with 24 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View file

@ -1848,9 +1848,16 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index)
inst_base->br = NON_BRANCH;
inst_cream->inst = inst;
if (I_BIT == 0) {
if (BITS(inst, 25, 27) == 2) {
inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
} else if (BITS(inst, 25, 27) == 3) {
inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
} else {
// Reaching this would indicate the thumb version
// of this instruction, however the 3DS CPU doesn't
// support this variant (the 3DS CPU is only ARMv6K,
// while this variant is added in ARMv6T2).
// So it's sufficient for citra to not implement this.
DEBUG_MSG;
}
@ -2800,9 +2807,16 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
inst_base->br = NON_BRANCH;
inst_cream->inst = inst;
if (I_BIT == 0) {
if (BITS(inst, 25, 27) == 2) {
inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
} else if (BITS(inst, 25, 27) == 3) {
inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
} else {
// Reaching this would indicate the thumb version
// of this instruction, however the 3DS CPU doesn't
// support this variant (the 3DS CPU is only ARMv6K,
// while this variant is added in ARMv6T2).
// So it's sufficient for citra to not implement this.
DEBUG_MSG;
}