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Merge pull request #9010 from liamwhite/buttwise
macro_jit_x64: fix miscompilation of bit extraction operations
This commit is contained in:
commit
92c0ad23eb
1 changed files with 9 additions and 37 deletions
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@ -279,28 +279,13 @@ void MacroJITx64Impl::Compile_ExtractInsert(Macro::Opcode opcode) {
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auto dst = Compile_GetRegister(opcode.src_a, RESULT);
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auto dst = Compile_GetRegister(opcode.src_a, RESULT);
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auto src = Compile_GetRegister(opcode.src_b, eax);
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auto src = Compile_GetRegister(opcode.src_b, eax);
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if (opcode.bf_src_bit != 0 && opcode.bf_src_bit != 31) {
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shr(src, opcode.bf_src_bit);
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} else if (opcode.bf_src_bit == 31) {
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xor_(src, src);
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}
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// Don't bother masking the whole register since we're using a 32 bit register
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if (opcode.bf_size != 31 && opcode.bf_size != 0) {
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and_(src, opcode.GetBitfieldMask());
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} else if (opcode.bf_size == 0) {
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xor_(src, src);
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}
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if (opcode.bf_dst_bit != 31 && opcode.bf_dst_bit != 0) {
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shl(src, opcode.bf_dst_bit);
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} else if (opcode.bf_dst_bit == 31) {
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xor_(src, src);
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}
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const u32 mask = ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit);
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const u32 mask = ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit);
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if (mask != 0xffffffff) {
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and_(dst, mask);
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and_(dst, mask);
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shr(src, opcode.bf_src_bit);
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}
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and_(src, opcode.GetBitfieldMask());
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shl(src, opcode.bf_dst_bit);
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or_(dst, src);
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or_(dst, src);
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Compile_ProcessResult(opcode.result_operation, opcode.dst);
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Compile_ProcessResult(opcode.result_operation, opcode.dst);
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}
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}
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@ -309,17 +294,9 @@ void MacroJITx64Impl::Compile_ExtractShiftLeftImmediate(Macro::Opcode opcode) {
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const auto src = Compile_GetRegister(opcode.src_b, RESULT);
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const auto src = Compile_GetRegister(opcode.src_b, RESULT);
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shr(src, dst.cvt8());
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shr(src, dst.cvt8());
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if (opcode.bf_size != 0 && opcode.bf_size != 31) {
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and_(src, opcode.GetBitfieldMask());
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and_(src, opcode.GetBitfieldMask());
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shl(src, opcode.bf_dst_bit);
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} else if (opcode.bf_size == 0) {
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xor_(src, src);
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}
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if (opcode.bf_dst_bit != 0 && opcode.bf_dst_bit != 31) {
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shl(src, opcode.bf_dst_bit);
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} else if (opcode.bf_dst_bit == 31) {
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xor_(src, src);
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}
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Compile_ProcessResult(opcode.result_operation, opcode.dst);
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Compile_ProcessResult(opcode.result_operation, opcode.dst);
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}
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}
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@ -327,13 +304,8 @@ void MacroJITx64Impl::Compile_ExtractShiftLeftRegister(Macro::Opcode opcode) {
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const auto dst = Compile_GetRegister(opcode.src_a, ecx);
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const auto dst = Compile_GetRegister(opcode.src_a, ecx);
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const auto src = Compile_GetRegister(opcode.src_b, RESULT);
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const auto src = Compile_GetRegister(opcode.src_b, RESULT);
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if (opcode.bf_src_bit != 0) {
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shr(src, opcode.bf_src_bit);
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shr(src, opcode.bf_src_bit);
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and_(src, opcode.GetBitfieldMask());
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}
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if (opcode.bf_size != 31) {
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and_(src, opcode.GetBitfieldMask());
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}
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shl(src, dst.cvt8());
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shl(src, dst.cvt8());
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Compile_ProcessResult(opcode.result_operation, opcode.dst);
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Compile_ProcessResult(opcode.result_operation, opcode.dst);
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