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https://git.suyu.dev/suyu/suyu.git
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vk_shader_decompiler: Misc fixes
Fix missing OpSelectionMerge instruction. This caused devices loses on most hardware, Intel didn't care. Fix [-1;1] -> [0;1] depth conversions. Conditionally use VK_EXT_scalar_block_layout. This allows us to use non-std140 layouts on UBOs. Update external Vulkan headers.
This commit is contained in:
ReinUsesLisp
parent
dec3c981d0
commit
a4c5e3e339
3 changed files with 68 additions and 46 deletions
2
externals/Vulkan-Headers
vendored
2
externals/Vulkan-Headers
vendored
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@ -1 +1 @@
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Subproject commit 15e5c4db7500b936ae758236f2e72fc1aec22020
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Subproject commit d05c8df88da98ec1ab3bc600d7f5783b4060895b
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@ -17,6 +17,7 @@
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/engines/shader_header.h"
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#include "video_core/renderer_vulkan/vk_device.h"
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#include "video_core/renderer_vulkan/vk_shader_decompiler.h"
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#include "video_core/shader/shader_ir.h"
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@ -33,7 +34,8 @@ using ShaderStage = Tegra::Engines::Maxwell3D::Regs::ShaderStage;
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using Operation = const OperationNode&;
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// TODO(Rodrigo): Use rasterizer's value
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constexpr u32 MAX_CONSTBUFFER_ELEMENTS = 0x1000;
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constexpr u32 MAX_CONSTBUFFER_FLOATS = 0x4000;
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constexpr u32 MAX_CONSTBUFFER_ELEMENTS = MAX_CONSTBUFFER_FLOATS / 4;
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constexpr u32 STAGE_BINDING_STRIDE = 0x100;
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enum class Type { Bool, Bool2, Float, Int, Uint, HalfFloat };
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@ -87,8 +89,8 @@ bool IsPrecise(Operation operand) {
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class SPIRVDecompiler : public Sirit::Module {
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public:
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explicit SPIRVDecompiler(const ShaderIR& ir, ShaderStage stage)
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: Module(0x00010300), ir{ir}, stage{stage}, header{ir.GetHeader()} {
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explicit SPIRVDecompiler(const VKDevice& device, const ShaderIR& ir, ShaderStage stage)
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: Module(0x00010300), device{device}, ir{ir}, stage{stage}, header{ir.GetHeader()} {
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AddCapability(spv::Capability::Shader);
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AddExtension("SPV_KHR_storage_buffer_storage_class");
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AddExtension("SPV_KHR_variable_pointers");
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@ -195,7 +197,9 @@ public:
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entries.samplers.emplace_back(sampler);
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}
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for (const auto& attribute : ir.GetInputAttributes()) {
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entries.attributes.insert(GetGenericAttributeLocation(attribute));
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if (IsGenericAttribute(attribute)) {
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entries.attributes.insert(GetGenericAttributeLocation(attribute));
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}
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}
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entries.clip_distances = ir.GetClipDistances();
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entries.shader_length = ir.GetLength();
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@ -210,7 +214,6 @@ private:
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std::array<OperationDecompilerFn, static_cast<std::size_t>(OperationCode::Amount)>;
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static constexpr auto INTERNAL_FLAGS_COUNT = static_cast<std::size_t>(InternalFlag::Amount);
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static constexpr u32 CBUF_STRIDE = 16;
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void AllocateBindings() {
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const u32 binding_base = static_cast<u32>(stage) * STAGE_BINDING_STRIDE;
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@ -315,6 +318,7 @@ private:
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constexpr std::array<const char*, INTERNAL_FLAGS_COUNT> names = {"zero", "sign", "carry",
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"overflow"};
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for (std::size_t flag = 0; flag < INTERNAL_FLAGS_COUNT; ++flag) {
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const auto flag_code = static_cast<InternalFlag>(flag);
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const Id id = OpVariable(t_prv_bool, spv::StorageClass::Private, v_false);
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internal_flags[flag] = AddGlobalVariable(Name(id, names[flag]));
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}
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@ -374,7 +378,9 @@ private:
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u32 binding = const_buffers_base_binding;
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for (const auto& entry : ir.GetConstantBuffers()) {
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const auto [index, size] = entry;
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const Id id = OpVariable(t_cbuf_ubo, spv::StorageClass::Uniform);
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const Id type =
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device.IsExtScalarBlockLayoutSupported() ? t_cbuf_scalar_ubo : t_cbuf_std140_ubo;
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const Id id = OpVariable(type, spv::StorageClass::Uniform);
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AddGlobalVariable(Name(id, fmt::format("cbuf_{}", index)));
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Decorate(id, spv::Decoration::Binding, binding++);
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@ -569,33 +575,35 @@ private:
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const Node offset = cbuf->GetOffset();
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const Id buffer_id = constant_buffers.at(cbuf->GetIndex());
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Id buffer_index{};
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Id buffer_element{};
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if (const auto immediate = std::get_if<ImmediateNode>(offset)) {
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// Direct access
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const u32 offset_imm = immediate->GetValue();
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ASSERT(offset_imm % 4 == 0);
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buffer_index = Constant(t_uint, offset_imm / 16);
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buffer_element = Constant(t_uint, (offset_imm / 4) % 4);
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} else if (std::holds_alternative<OperationNode>(*offset)) {
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// Indirect access
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// TODO(Rodrigo): Use a uniform buffer stride of 4 and drop this slow math (which
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// emits sub-optimal code on GLSL from my testing).
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const Id offset_id = BitcastTo<Type::Uint>(Visit(offset));
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const Id unsafe_offset = Emit(OpUDiv(t_uint, offset_id, Constant(t_uint, 4)));
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const Id final_offset = Emit(
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OpUMod(t_uint, unsafe_offset, Constant(t_uint, MAX_CONSTBUFFER_ELEMENTS - 1)));
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buffer_index = Emit(OpUDiv(t_uint, final_offset, Constant(t_uint, 4)));
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buffer_element = Emit(OpUMod(t_uint, final_offset, Constant(t_uint, 4)));
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Id pointer{};
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if (device.IsExtScalarBlockLayoutSupported()) {
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const Id buffer_offset = Emit(OpShiftRightLogical(
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t_uint, BitcastTo<Type::Uint>(Visit(offset)), Constant(t_uint, 2u)));
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pointer = Emit(
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OpAccessChain(t_cbuf_float, buffer_id, Constant(t_uint, 0u), buffer_offset));
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} else {
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UNREACHABLE_MSG("Unmanaged offset node type");
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Id buffer_index{};
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Id buffer_element{};
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if (const auto immediate = std::get_if<ImmediateNode>(offset)) {
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// Direct access
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const u32 offset_imm = immediate->GetValue();
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ASSERT(offset_imm % 4 == 0);
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buffer_index = Constant(t_uint, offset_imm / 16);
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buffer_element = Constant(t_uint, (offset_imm / 4) % 4);
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} else if (std::holds_alternative<OperationNode>(*offset)) {
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// Indirect access
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const Id offset_id = BitcastTo<Type::Uint>(Visit(offset));
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const Id unsafe_offset = Emit(OpUDiv(t_uint, offset_id, Constant(t_uint, 4)));
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const Id final_offset = Emit(OpUMod(
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t_uint, unsafe_offset, Constant(t_uint, MAX_CONSTBUFFER_ELEMENTS - 1)));
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buffer_index = Emit(OpUDiv(t_uint, final_offset, Constant(t_uint, 4)));
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buffer_element = Emit(OpUMod(t_uint, final_offset, Constant(t_uint, 4)));
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} else {
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UNREACHABLE_MSG("Unmanaged offset node type");
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}
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pointer = Emit(OpAccessChain(t_cbuf_float, buffer_id, Constant(t_uint, 0),
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buffer_index, buffer_element));
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}
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const Id pointer = Emit(OpAccessChain(t_cbuf_float, buffer_id, Constant(t_uint, 0),
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buffer_index, buffer_element));
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return Emit(OpLoad(t_float, pointer));
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} else if (const auto gmem = std::get_if<GmemNode>(node)) {
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@ -612,7 +620,9 @@ private:
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// It's invalid to call conditional on nested nodes, use an operation instead
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const Id true_label = OpLabel();
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const Id skip_label = OpLabel();
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Emit(OpBranchConditional(Visit(conditional->GetCondition()), true_label, skip_label));
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const Id condition = Visit(conditional->GetCondition());
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Emit(OpSelectionMerge(skip_label, spv::SelectionControlMask::MaskNone));
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Emit(OpBranchConditional(condition, true_label, skip_label));
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Emit(true_label);
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VisitBasicBlock(conditional->GetCode());
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@ -968,11 +978,11 @@ private:
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case ShaderStage::Vertex: {
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// TODO(Rodrigo): We should use VK_EXT_depth_range_unrestricted instead, but it doesn't
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// seem to be working on Nvidia's drivers and Intel (mesa and blob) doesn't support it.
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const Id position = AccessElement(t_float4, per_vertex, position_index);
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Id depth = Emit(OpLoad(t_float, AccessElement(t_out_float, position, 2)));
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const Id z_pointer = AccessElement(t_out_float, per_vertex, position_index, 2u);
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Id depth = Emit(OpLoad(t_float, z_pointer));
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depth = Emit(OpFAdd(t_float, depth, Constant(t_float, 1.0f)));
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depth = Emit(OpFMul(t_float, depth, Constant(t_float, 0.5f)));
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Emit(OpStore(AccessElement(t_out_float, position, 2), depth));
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Emit(OpStore(z_pointer, depth));
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break;
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}
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case ShaderStage::Fragment: {
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@ -1293,6 +1303,7 @@ private:
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&SPIRVDecompiler::YNegate,
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};
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const VKDevice& device;
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const ShaderIR& ir;
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const ShaderStage stage;
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const Tegra::Shader::Header header;
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@ -1331,12 +1342,18 @@ private:
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const Id t_out_float4 = Name(TypePointer(spv::StorageClass::Output, t_float4), "out_float4");
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const Id t_cbuf_float = TypePointer(spv::StorageClass::Uniform, t_float);
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const Id t_cbuf_array =
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Decorate(Name(TypeArray(t_float4, Constant(t_uint, MAX_CONSTBUFFER_ELEMENTS)), "CbufArray"),
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spv::Decoration::ArrayStride, CBUF_STRIDE);
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const Id t_cbuf_struct = MemberDecorate(
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Decorate(TypeStruct(t_cbuf_array), spv::Decoration::Block), 0, spv::Decoration::Offset, 0);
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const Id t_cbuf_ubo = TypePointer(spv::StorageClass::Uniform, t_cbuf_struct);
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const Id t_cbuf_std140 = Decorate(
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Name(TypeArray(t_float4, Constant(t_uint, MAX_CONSTBUFFER_ELEMENTS)), "CbufStd140Array"),
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spv::Decoration::ArrayStride, 16u);
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const Id t_cbuf_scalar = Decorate(
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Name(TypeArray(t_float, Constant(t_uint, MAX_CONSTBUFFER_FLOATS)), "CbufScalarArray"),
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spv::Decoration::ArrayStride, 4u);
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const Id t_cbuf_std140_struct = MemberDecorate(
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Decorate(TypeStruct(t_cbuf_std140), spv::Decoration::Block), 0, spv::Decoration::Offset, 0);
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const Id t_cbuf_scalar_struct = MemberDecorate(
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Decorate(TypeStruct(t_cbuf_scalar), spv::Decoration::Block), 0, spv::Decoration::Offset, 0);
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const Id t_cbuf_std140_ubo = TypePointer(spv::StorageClass::Uniform, t_cbuf_std140_struct);
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const Id t_cbuf_scalar_ubo = TypePointer(spv::StorageClass::Uniform, t_cbuf_scalar_struct);
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const Id t_gmem_float = TypePointer(spv::StorageClass::StorageBuffer, t_float);
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const Id t_gmem_array =
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@ -1385,8 +1402,9 @@ private:
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std::map<u32, Id> labels;
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};
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DecompilerResult Decompile(const VideoCommon::Shader::ShaderIR& ir, Maxwell::ShaderStage stage) {
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auto decompiler = std::make_unique<SPIRVDecompiler>(ir, stage);
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DecompilerResult Decompile(const VKDevice& device, const VideoCommon::Shader::ShaderIR& ir,
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Maxwell::ShaderStage stage) {
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auto decompiler = std::make_unique<SPIRVDecompiler>(device, ir, stage);
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decompiler->Decompile();
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return {std::move(decompiler), decompiler->GetShaderEntries()};
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}
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@ -20,10 +20,13 @@ namespace VideoCommon::Shader {
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class ShaderIR;
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}
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namespace Vulkan {
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class VKDevice;
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}
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namespace Vulkan::VKShader {
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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using SamplerEntry = VideoCommon::Shader::Sampler;
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constexpr u32 DESCRIPTOR_SET = 0;
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@ -75,6 +78,7 @@ struct ShaderEntries {
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using DecompilerResult = std::pair<std::unique_ptr<Sirit::Module>, ShaderEntries>;
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DecompilerResult Decompile(const VideoCommon::Shader::ShaderIR& ir, Maxwell::ShaderStage stage);
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DecompilerResult Decompile(const VKDevice& device, const VideoCommon::Shader::ShaderIR& ir,
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Maxwell::ShaderStage stage);
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} // namespace Vulkan::VKShader
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