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dyncom: Implement missing shifts in ScaledRegisterPostIndexed, etc

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This commit is contained in:
Lioncash 2015-01-18 17:31:39 -05:00
parent 1cb31f4f06
commit a873f157d0
1 changed files with 33 additions and 7 deletions
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38
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -410,10 +410,21 @@ void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, un
}
break;
case 2:
DEBUG_MSG;
if (shift_imm == 0) { // ASR #32
if (BIT(rm, 31) == 1)
index = 0xFFFFFFFF;
else
index = 0;
} else {
index = static_cast<int>(rm) >> shift_imm;
}
break;
case 3:
DEBUG_MSG;
if (shift_imm == 0) {
index = (cpu->CFlag << 31) | (rm >> 1);
} else {
index = ROTATE_RIGHT_32(rm, shift_imm);
}
break;
}
@ -449,10 +460,21 @@ void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, u
}
break;
case 2:
DEBUG_MSG;
if (shift_imm == 0) { // ASR #32
if (BIT(rm, 31) == 1)
index = 0xFFFFFFFF;
else
index = 0;
} else {
index = static_cast<int>(rm) >> shift_imm;
}
break;
case 3:
DEBUG_MSG;
if (shift_imm == 0) {
index = (cpu->CFlag << 31) | (rm >> 1);
} else {
index = ROTATE_RIGHT_32(rm, shift_imm);
}
break;
}
@ -655,7 +677,7 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign
break;
case 2:
if (shift_imm == 0) { // ASR #32
if (rm >> 31)
if (BIT(rm, 31) == 1)
index = 0xFFFFFFFF;
else
index = 0;
@ -664,7 +686,11 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign
}
break;
case 3:
DEBUG_MSG;
if (shift_imm == 0) {
index = (cpu->CFlag << 31) | (rm >> 1);
} else {
index = ROTATE_RIGHT_32(rm, shift_imm);
}
break;
}