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https://git.suyu.dev/suyu/suyu.git
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Remove SyncAlphaTest and clang format
This commit is contained in:
parent
7b39107e3a
commit
bcb5b924fd
4 changed files with 9 additions and 8 deletions
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@ -572,8 +572,8 @@ void RasterizerOpenGL::DrawArrays() {
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SyncBlendState();
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SyncBlendState();
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SyncLogicOpState();
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SyncLogicOpState();
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SyncCullMode();
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SyncCullMode();
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SyncAlphaTest();
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SyncScissorTest();
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SyncScissorTest();
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// Alpha Testing is synced on shaders.
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SyncTransformFeedback();
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SyncTransformFeedback();
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SyncPointState();
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SyncPointState();
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@ -886,7 +886,7 @@ void RasterizerOpenGL::SetupAlphaTesting(Shader& shader) {
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const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs;
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const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs;
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glProgramUniform1ui(shader->GetProgramHandle(), shader->GetAlphaTestingEnableLocation(),
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glProgramUniform1ui(shader->GetProgramHandle(), shader->GetAlphaTestingEnableLocation(),
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regs.alpha_test_enabled);
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regs.alpha_test_enabled);
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glProgramUniform1f(shader->GetProgramHandle(), shader->GetAlphaTestingRefLocation(),
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glProgramUniform1f(shader->GetProgramHandle(), shader->GetAlphaTestingRefLocation(),
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regs.alpha_test_ref);
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regs.alpha_test_ref);
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@ -1026,6 +1026,7 @@ void RasterizerOpenGL::SyncLogicOpState() {
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state.logic_op.operation = MaxwellToGL::LogicOp(regs.logic_op.operation);
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state.logic_op.operation = MaxwellToGL::LogicOp(regs.logic_op.operation);
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}
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}
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<<<<<<< HEAD
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void RasterizerOpenGL::SyncAlphaTest() {
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void RasterizerOpenGL::SyncAlphaTest() {
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const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs;
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const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs;
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@ -1053,6 +1054,8 @@ void RasterizerOpenGL::SyncScissorTest() {
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}
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}
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}
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}
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=======
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>>>>>>> Remove SyncAlphaTest and clang format
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void RasterizerOpenGL::SyncTransformFeedback() {
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void RasterizerOpenGL::SyncTransformFeedback() {
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const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs;
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const auto& regs = Core::System::GetInstance().GPU().Maxwell3D().regs;
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@ -132,6 +132,7 @@ private:
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u32 SetupTextures(Tegra::Engines::Maxwell3D::Regs::ShaderStage stage, Shader& shader,
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u32 SetupTextures(Tegra::Engines::Maxwell3D::Regs::ShaderStage stage, Shader& shader,
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GLenum primitive_mode, u32 current_unit);
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GLenum primitive_mode, u32 current_unit);
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/// Syncs the alpha test state to match the guest state
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void SetupAlphaTesting(Shader& shader);
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void SetupAlphaTesting(Shader& shader);
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/// Syncs the viewport to match the guest state
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/// Syncs the viewport to match the guest state
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@ -164,9 +165,6 @@ private:
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/// Syncs the LogicOp state to match the guest state
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/// Syncs the LogicOp state to match the guest state
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void SyncLogicOpState();
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void SyncLogicOpState();
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/// Syncs the alpha test state to match the guest state
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void SyncAlphaTest();
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/// Syncs the scissor test state to match the guest state
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/// Syncs the scissor test state to match the guest state
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void SyncScissorTest();
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void SyncScissorTest();
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@ -73,7 +73,6 @@ public:
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/// Gets the GL uniform location for the specified resource, caching as needed
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/// Gets the GL uniform location for the specified resource, caching as needed
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GLint GetUniformLocation(const GLShader::SamplerEntry& sampler);
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GLint GetUniformLocation(const GLShader::SamplerEntry& sampler);
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GLint GetAlphaTestingEnableLocation();
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GLint GetAlphaTestingEnableLocation();
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GLint GetAlphaTestingFuncLocation();
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GLint GetAlphaTestingFuncLocation();
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GLint GetAlphaTestingRefLocation();
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GLint GetAlphaTestingRefLocation();
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@ -1280,8 +1280,9 @@ private:
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header.ps.IsColorComponentOutputEnabled(render_target, 1) ||
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header.ps.IsColorComponentOutputEnabled(render_target, 1) ||
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header.ps.IsColorComponentOutputEnabled(render_target, 2) ||
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header.ps.IsColorComponentOutputEnabled(render_target, 2) ||
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header.ps.IsColorComponentOutputEnabled(render_target, 3)) {
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header.ps.IsColorComponentOutputEnabled(render_target, 3)) {
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shader.AddLine(fmt::format("if (AlphaFunc({}, alpha_testing_ref, alpha_testing_func)) discard;",
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shader.AddLine(fmt::format(
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regs.GetRegisterAsFloat(current_reg)));
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"if (AlphaFunc({}, alpha_testing_ref, alpha_testing_func)) discard;",
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regs.GetRegisterAsFloat(current_reg)));
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current_reg += 4;
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current_reg += 4;
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}
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}
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}
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}
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