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https://git.suyu.dev/suyu/suyu.git
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shader: Add support for native 16-bit floats
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parent
376aa94819
commit
cbbca26d18
9 changed files with 50 additions and 14 deletions
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@ -211,6 +211,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/translate.h
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frontend/maxwell/translate_program.cpp
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frontend/maxwell/translate_program.h
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host_translate_info.h
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ir_opt/collect_shader_info_pass.cpp
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ir_opt/constant_propagation_pass.cpp
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ir_opt/dead_code_elimination_pass.cpp
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@ -13,6 +13,7 @@
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#include "shader_recompiler/frontend/maxwell/structured_control_flow.h"
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#include "shader_recompiler/frontend/maxwell/translate/translate.h"
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#include "shader_recompiler/frontend/maxwell/translate_program.h"
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#include "shader_recompiler/host_translate_info.h"
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#include "shader_recompiler/ir_opt/passes.h"
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namespace Shader::Maxwell {
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@ -120,7 +121,7 @@ void AddNVNStorageBuffers(IR::Program& program) {
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} // Anonymous namespace
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IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
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Environment& env, Flow::CFG& cfg) {
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Environment& env, Flow::CFG& cfg, const HostTranslateInfo& host_info) {
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IR::Program program;
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program.syntax_list = BuildASL(inst_pool, block_pool, env, cfg);
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program.blocks = GenerateBlocks(program.syntax_list);
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@ -150,8 +151,9 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
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RemoveUnreachableBlocks(program);
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// Replace instructions before the SSA rewrite
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Optimization::LowerFp16ToFp32(program);
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if (!host_info.support_float16) {
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Optimization::LowerFp16ToFp32(program);
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}
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Optimization::SsaRewritePass(program);
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Optimization::GlobalMemoryToStorageBufferPass(program);
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@ -8,13 +8,14 @@
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/frontend/maxwell/control_flow.h"
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#include "shader_recompiler/host_translate_info.h"
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#include "shader_recompiler/object_pool.h"
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namespace Shader::Maxwell {
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[[nodiscard]] IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool,
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ObjectPool<IR::Block>& block_pool, Environment& env,
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Flow::CFG& cfg);
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Flow::CFG& cfg, const HostTranslateInfo& host_info);
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[[nodiscard]] IR::Program MergeDualVertexPrograms(IR::Program& vertex_a, IR::Program& vertex_b,
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Environment& env_vertex_b);
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18
src/shader_recompiler/host_translate_info.h
Normal file
18
src/shader_recompiler/host_translate_info.h
Normal file
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@ -0,0 +1,18 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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namespace Shader {
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// Try to keep entries here to a minimum
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// They can accidentally change the cached information in a shader
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/// Misc information about the host
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struct HostTranslateInfo {
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bool support_float16{}; ///< True when the device supports 16-bit floats
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bool support_int64{}; ///< True when the device supports 64-bit integers
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};
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} // namespace Shader
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@ -201,6 +201,10 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
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.has_gl_component_indexing_bug = device.HasComponentIndexingBug(),
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.has_gl_precise_bug = device.HasPreciseBug(),
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.ignore_nan_fp_comparisons = true,
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},
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host_info{
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.support_float16 = false,
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.support_int64 = true,
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} {
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if (use_asynchronous_shaders) {
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workers = CreateWorkers();
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@ -373,15 +377,15 @@ std::unique_ptr<GraphicsPipeline> ShaderCache::CreateGraphicsPipeline(
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Shader::Maxwell::Flow::CFG cfg(env, pools.flow_block, cfg_offset, index == 0);
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if (!uses_vertex_a || index != 1) {
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// Normal path
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programs[index] = TranslateProgram(pools.inst, pools.block, env, cfg);
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programs[index] = TranslateProgram(pools.inst, pools.block, env, cfg, host_info);
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for (const auto& desc : programs[index].info.storage_buffers_descriptors) {
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total_storage_buffers += desc.count;
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}
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} else {
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// VertexB path when VertexA is present.
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Shader::IR::Program& program_va{programs[0]};
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Shader::IR::Program program_vb{TranslateProgram(pools.inst, pools.block, env, cfg)};
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auto& program_va{programs[0]};
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auto program_vb{TranslateProgram(pools.inst, pools.block, env, cfg, host_info)};
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for (const auto& desc : program_vb.info.storage_buffers_descriptors) {
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total_storage_buffers += desc.count;
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}
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@ -449,7 +453,7 @@ std::unique_ptr<ComputePipeline> ShaderCache::CreateComputePipeline(
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LOG_INFO(Render_OpenGL, "0x{:016x}", key.Hash());
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Shader::Maxwell::Flow::CFG cfg{env, pools.flow_block, env.StartAddress()};
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Shader::IR::Program program{TranslateProgram(pools.inst, pools.block, env, cfg)};
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auto program{TranslateProgram(pools.inst, pools.block, env, cfg, host_info)};
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u32 num_storage_buffers{};
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for (const auto& desc : program.info.storage_buffers_descriptors) {
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@ -14,6 +14,7 @@
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#include "common/common_types.h"
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#include "common/thread_worker.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#include "shader_recompiler/host_translate_info.h"
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#include "shader_recompiler/object_pool.h"
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#include "video_core/engines/shader_type.h"
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#include "video_core/renderer_opengl/gl_compute_pipeline.h"
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@ -82,6 +83,8 @@ private:
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std::unordered_map<ComputePipelineKey, std::unique_ptr<ComputePipeline>> compute_cache;
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Shader::Profile profile;
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Shader::HostTranslateInfo host_info;
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std::filesystem::path shader_cache_filename;
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std::unique_ptr<ShaderWorker> workers;
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};
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@ -307,6 +307,10 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, Tegra::Engines::Maxw
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.has_broken_signed_operations = false,
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.ignore_nan_fp_comparisons = false,
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};
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host_info = Shader::HostTranslateInfo{
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.support_float16 = device.IsFloat16Supported(),
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.support_int64 = true,
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};
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}
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PipelineCache::~PipelineCache() = default;
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@ -484,11 +488,11 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline(
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Shader::Maxwell::Flow::CFG cfg(env, pools.flow_block, cfg_offset, index == 0);
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if (!uses_vertex_a || index != 1) {
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// Normal path
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programs[index] = TranslateProgram(pools.inst, pools.block, env, cfg);
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programs[index] = TranslateProgram(pools.inst, pools.block, env, cfg, host_info);
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} else {
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// VertexB path when VertexA is present.
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Shader::IR::Program& program_va{programs[0]};
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Shader::IR::Program program_vb{TranslateProgram(pools.inst, pools.block, env, cfg)};
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auto& program_va{programs[0]};
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auto program_vb{TranslateProgram(pools.inst, pools.block, env, cfg, host_info)};
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programs[index] = MergeDualVertexPrograms(program_va, program_vb, env);
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}
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}
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@ -575,7 +579,7 @@ std::unique_ptr<ComputePipeline> PipelineCache::CreateComputePipeline(
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LOG_INFO(Render_Vulkan, "0x{:016x}", key.Hash());
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Shader::Maxwell::Flow::CFG cfg{env, pools.flow_block, env.StartAddress()};
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Shader::IR::Program program{TranslateProgram(pools.inst, pools.block, env, cfg)};
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auto program{TranslateProgram(pools.inst, pools.block, env, cfg, host_info)};
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const std::vector<u32> code{EmitSPIRV(profile, program)};
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device.SaveShader(code);
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vk::ShaderModule spv_module{BuildShader(device, code)};
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@ -19,6 +19,7 @@
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#include "shader_recompiler/frontend/maxwell/control_flow.h"
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#include "shader_recompiler/host_translate_info.h"
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#include "shader_recompiler/object_pool.h"
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#include "shader_recompiler/profile.h"
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#include "video_core/engines/maxwell_3d.h"
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@ -157,6 +158,8 @@ private:
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ShaderPools main_pools;
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Shader::Profile profile;
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Shader::HostTranslateInfo host_info;
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std::filesystem::path pipeline_cache_filename;
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Common::ThreadWorker workers;
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@ -497,8 +497,8 @@ Device::Device(VkInstance instance_, vk::PhysicalDevice physical_, VkSurfaceKHR
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}
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if (is_float16_supported && driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS) {
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// Intel's compiler crashes when using fp16 on Astral Chain, disable it for the time being.
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// LOG_WARNING(Render_Vulkan, "Blacklisting Intel proprietary from float16 math");
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// is_float16_supported = false;
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LOG_WARNING(Render_Vulkan, "Blacklisting Intel proprietary from float16 math");
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is_float16_supported = false;
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}
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graphics_queue = logical.GetQueue(graphics_family);
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