mirror of
https://git.suyu.dev/suyu/suyu.git
synced 2024-11-26 16:52:46 +01:00
bunnei
commit
dbff4e5e12
14 changed files with 36 additions and 370 deletions
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@ -110,13 +110,11 @@ set(HEADERS
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arm/dyncom/arm_dyncom_thumb.h
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arm/interpreter/arm_interpreter.h
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arm/skyeye_common/arm_regformat.h
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arm/skyeye_common/armcpu.h
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arm/skyeye_common/armdefs.h
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arm/skyeye_common/armemu.h
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arm/skyeye_common/armmmu.h
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arm/skyeye_common/armos.h
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arm/skyeye_common/skyeye_defs.h
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arm/skyeye_common/skyeye_types.h
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arm/skyeye_common/vfp/asm_vfp.h
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arm/skyeye_common/vfp/vfp.h
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arm/skyeye_common/vfp/vfp_helper.h
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@ -2,7 +2,6 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/arm/skyeye_common/armcpu.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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@ -6,14 +6,6 @@
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#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1))
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#define BIT(n) ((instr >> (n)) & 1)
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#define BAD do { printf("meet BAD at %s, instr is %x\n", __FUNCTION__, instr ); } while(0);
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#define ptr_N cpu->ptr_N
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#define ptr_Z cpu->ptr_Z
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#define ptr_C cpu->ptr_C
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#define ptr_V cpu->ptr_V
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#define ptr_I cpu->ptr_I
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#define ptr_T cpu->ptr_T
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#define ptr_CPSR cpu->ptr_gpr[16]
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// For MUL instructions
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#define RDHi ((instr >> 16) & 0xF)
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@ -49,24 +41,6 @@
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#define SBIT BIT(20)
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#define DESTReg (BITS (12, 15))
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// They are in unused state, give a corrent value when using
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#define IS_V5E 0
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#define IS_V5 0
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#define IS_V6 0
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#define LHSReg 0
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// Temp define the using the pc reg need implement a flow
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#define STORE_CHECK_RD_PC ADD(R(RD), CONST(INSTR_SIZE * 2))
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#define OPERAND operand(cpu,instr,bb,NULL)
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#define SCO_OPERAND(sco) operand(cpu,instr,bb,sco)
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#define BOPERAND boperand(instr)
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#define CHECK_RN_PC (RN == 15 ? ADD(AND(R(RN), CONST(~0x1)), CONST(INSTR_SIZE * 2)) : R(RN))
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#define CHECK_RN_PC_WA (RN == 15 ? ADD(AND(R(RN), CONST(~0x3)), CONST(INSTR_SIZE * 2)) : R(RN))
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#define GET_USER_MODE() (OR(ICMP_EQ(R(MODE_REG), CONST(USER32MODE)), ICMP_EQ(R(MODE_REG), CONST(SYSTEM32MODE))))
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int decode_arm_instr(uint32_t instr, int32_t *idx);
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enum DECODE_STATUS {
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@ -83,23 +57,8 @@ struct instruction_set_encoding_item {
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typedef struct instruction_set_encoding_item ISEITEM;
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#define RECORD_WB(value, flag) { cpu->dyncom_engine->wb_value = value;cpu->dyncom_engine->wb_flag = flag; }
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#define INIT_WB(wb_value, wb_flag) RECORD_WB(wb_value, wb_flag)
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#define EXECUTE_WB(base_reg) { if(cpu->dyncom_engine->wb_flag) LET(base_reg, cpu->dyncom_engine->wb_value); }
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inline int get_reg_count(uint32_t instr) {
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int i = BITS(0, 15);
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int count = 0;
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while (i) {
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if (i & 1)
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count++;
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i = i >> 1;
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}
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return count;
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}
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enum ARMVER {
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// ARM versions
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enum {
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INVALID = 0,
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ARMALL,
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ARMV4,
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@ -16,10 +16,7 @@
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*
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*/
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#ifndef __ARM_DYNCOM_RUN__
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#define __ARM_DYNCOM_RUN__
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#include "core/arm/skyeye_common/skyeye_types.h"
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#pragma once
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void switch_mode(arm_core_t *core, uint32_t mode);
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@ -51,5 +48,3 @@ static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn) {
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static inline u32 CHECK_READ_REG15(arm_core_t* core, int Rn) {
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return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn];
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}
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#endif
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@ -24,11 +24,9 @@
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* @date 2011-11-07
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*/
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#ifndef __ARM_DYNCOM_THUMB_H__
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#define __ARM_DYNCOM_THUMB_H__
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#pragma once
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/skyeye_types.h"
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enum tdstate {
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t_undefined, // Undefined Thumb instruction
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@ -47,5 +45,3 @@ static inline u32 get_thumb_instr(u32 instr, addr_t pc) {
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tinstr = instr & 0xFFFF;
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return tinstr;
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}
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#endif
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@ -1,7 +1,6 @@
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#ifndef __ARM_REGFORMAT_H__
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#define __ARM_REGFORMAT_H__
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#pragma once
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enum arm_regno{
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enum {
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R0 = 0,
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R1,
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R2,
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@ -20,7 +19,7 @@ enum arm_regno{
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R15, //PC,
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CPSR_REG,
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SPSR_REG,
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#if 1
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PHYS_PC,
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R13_USR,
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R14_USR,
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@ -95,11 +94,9 @@ enum arm_regno{
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VFP_FPSID = VFP_BASE,
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VFP_FPSCR,
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VFP_FPEXC,
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#endif
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MAX_REG_NUM,
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};
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#define CP15(idx) (idx - CP15_BASE)
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#define VFP_OFFSET(x) (x - VFP_BASE)
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#endif
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@ -1,78 +0,0 @@
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/*
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* arm
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* armcpu.h
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*
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* Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ARM_CPU_H__
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#define __ARM_CPU_H__
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#include <stddef.h>
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#include <stdio.h>
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#include "core/arm/skyeye_common/armdefs.h"
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typedef struct ARM_CPU_State_s {
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ARMul_State * core;
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uint32_t core_num;
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/* The core id that boot from
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*/
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uint32_t boot_core_id;
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}ARM_CPU_State;
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//static ARM_CPU_State* get_current_cpu(){
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// machine_config_t* mach = get_current_mach();
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// /* Casting a conf_obj_t to ARM_CPU_State type */
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// ARM_CPU_State* cpu = (ARM_CPU_State*)mach->cpu_data->obj;
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//
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// return cpu;
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//}
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/**
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* @brief Get the core instance boot from
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*
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* @return
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*/
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//static ARMul_State* get_boot_core(){
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// ARM_CPU_State* cpu = get_current_cpu();
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// return &cpu->core[cpu->boot_core_id];
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//}
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/**
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* @brief Get the instance of running core
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*
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* @return the core instance
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*/
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//static ARMul_State* get_current_core(){
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// /* Casting a conf_obj_t to ARM_CPU_State type */
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// int id = Common::CurrentThreadId();
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// /* If thread is not in running mode, we should give the boot core */
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// if(get_thread_state(id) != Running_state){
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// return get_boot_core();
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// }
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// /* Judge if we are running in paralell or sequenial */
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// if(thread_exist(id)){
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// conf_object_t* conf_obj = get_current_exec_priv(id);
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// return (ARMul_State*)get_cast_conf_obj(conf_obj, "arm_core_t");
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// }
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//
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// return NULL;
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//}
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#define CURRENT_CORE get_current_core()
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#endif
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@ -14,14 +14,10 @@
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef __ARMEMU_H__
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#define __ARMEMU_H__
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#pragma once
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#include "core/arm/skyeye_common/armdefs.h"
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//#include "skyeye.h"
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//extern ARMword isize;
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/* Shift Opcodes. */
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#define LSL 0
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@ -625,6 +621,3 @@ extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword);
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extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
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extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *);
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extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword);
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#endif
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@ -18,19 +18,10 @@
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ARMMMU_H_
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#define _ARMMMU_H_
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#pragma once
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#define WORD_SHT 2
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#define WORD_SIZE (1<<WORD_SHT)
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/* The MMU is accessible with MCR and MRC operations to copro 15: */
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#define MMU_COPRO (15)
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/* Register numbers in the MMU: */
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typedef enum mmu_regnum_t
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// Register numbers in the MMU
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enum
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{
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MMU_ID = 0,
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MMU_CONTROL = 1,
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@ -44,94 +35,22 @@ typedef enum mmu_regnum_t
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MMU_TLB_LOCKDOWN = 10,
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MMU_PID = 13,
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/*MMU_V4 */
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// MMU_V4
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MMU_V4_CACHE_OPS = 7,
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MMU_V4_TLB_OPS = 8,
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/*MMU_V3 */
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// MMU_V3
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MMU_V3_FLUSH_TLB = 5,
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MMU_V3_FLUSH_TLB_ENTRY = 6,
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MMU_V3_FLUSH_CACHE = 7,
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/*MMU Intel SA-1100 */
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// MMU Intel SA-1100
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MMU_SA_RB_OPS = 9,
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MMU_SA_DEBUG = 14,
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MMU_SA_CP15_R15 = 15,
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//chy 2003-08-24
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/*Intel xscale CP15 */
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// Intel xscale CP15
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XSCALE_CP15_CACHE_TYPE = 0,
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XSCALE_CP15_AUX_CONTROL = 1,
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XSCALE_CP15_COPRO_ACCESS = 15,
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} mmu_regnum_t;
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/* Bits in the control register */
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#define CONTROL_MMU (1<<0)
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#define CONTROL_ALIGN_FAULT (1<<1)
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#define CONTROL_CACHE (1<<2)
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#define CONTROL_DATA_CACHE (1<<2)
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#define CONTROL_WRITE_BUFFER (1<<3)
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#define CONTROL_BIG_ENDIAN (1<<7)
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#define CONTROL_SYSTEM (1<<8)
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#define CONTROL_ROM (1<<9)
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#define CONTROL_UNDEFINED (1<<10)
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#define CONTROL_BRANCH_PREDICT (1<<11)
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#define CONTROL_INSTRUCTION_CACHE (1<<12)
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#define CONTROL_VECTOR (1<<13)
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#define CONTROL_RR (1<<14)
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#define CONTROL_L4 (1<<15)
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#define CONTROL_XP (1<<23)
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#define CONTROL_EE (1<<25)
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/*Macro defines for MMU state*/
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#define MMU_CTL (state->mmu.control)
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#define MMU_Enabled (state->mmu.control & CONTROL_MMU)
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#define MMU_Disabled (!(MMU_Enabled))
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#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT)
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#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE)
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#define MMU_ICacheDisabled (!(MMU_ICacheDisabled))
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#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE)
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#define MMU_DCacheDisabled (!(MMU_DCacheEnabled))
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#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE)
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#define MMU_CacheDisabled (!(MMU_CacheEnabled))
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#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER)
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#define MMU_WBDisabled (!(MMU_WBEnabled))
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/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
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#define PID_VA_MAP_MASK 0xfe000000
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//#define mmu_pid_va_map(va) ({\
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// ARMword ret; \
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// if ((va) & PID_VA_MAP_MASK)\
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// ret = (va); \
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// else \
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// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
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// ret;\
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//})
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#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))
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/* FS[3:0] in the fault status register: */
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typedef enum fault_t
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{
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NO_FAULT = 0x0,
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ALIGNMENT_FAULT = 0x1,
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SECTION_TRANSLATION_FAULT = 0x5,
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PAGE_TRANSLATION_FAULT = 0x7,
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SECTION_DOMAIN_FAULT = 0x9,
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PAGE_DOMAIN_FAULT = 0xB,
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SECTION_PERMISSION_FAULT = 0xD,
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SUBPAGE_PERMISSION_FAULT = 0xF,
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/* defined by skyeye */
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TLB_READ_MISS = 0x30,
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TLB_WRITE_MISS = 0x40,
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} fault_t;
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#endif /* _ARMMMU_H_ */
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};
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|
|
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|
|
@ -13,26 +13,12 @@
|
|||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
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||||
#if FAST_MEMORY
|
||||
/* in user mode, mmap_base will be on initial brk,
|
||||
set at the first mmap request */
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||||
#define mmap_base -1
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#else
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#define mmap_base 0x50000000
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#endif
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static long mmap_next_base = mmap_base;
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||||
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||||
//static mmap_area_t* new_mmap_area(int sim_addr, int len);
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static char mmap_mem_write(short size, int addr, uint32_t value);
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static char mmap_mem_read(short size, int addr, uint32_t * value);
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||||
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/***************************************************************************\
|
||||
* SWI numbers *
|
||||
\***************************************************************************/
|
||||
//
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||||
// SWI Numbers
|
||||
//
|
||||
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||||
#define SWI_Syscall 0x0
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#define SWI_Exit 0x1
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|
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@ -58,15 +44,6 @@ static char mmap_mem_read(short size, int addr, uint32_t * value);
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#define SWI_ExitGroup 0xf8
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||||
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||||
#if 0
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||||
#define SWI_Time 0xd
|
||||
#define SWI_Clock 0x61
|
||||
#define SWI_Time 0x63
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#define SWI_Remove 0x64
|
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#define SWI_Rename 0x65
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#define SWI_Flen 0x6c
|
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#endif
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||||
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||||
#define SWI_Uname 0x7a
|
||||
#define SWI_Fcntl 0xdd
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||||
#define SWI_Fstat64 0xc5
|
||||
|
|
@ -75,57 +52,3 @@ static char mmap_mem_read(short size, int addr, uint32_t * value);
|
|||
|
||||
#define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */
|
||||
|
||||
/***************************************************************************\
|
||||
* SWI structures *
|
||||
\***************************************************************************/
|
||||
|
||||
/* Arm binaries (for now) only support 32 bit, and expect to receive
|
||||
32-bit compliant structure in return of a systen call. Because
|
||||
we use host system calls to emulate system calls, the returned
|
||||
structure can be 32-bit compliant or 64-bit compliant, depending
|
||||
on the OS running skyeye. Therefore, we need a fixed size structure
|
||||
adapted to arm.*/
|
||||
|
||||
/* Borrowed from qemu */
|
||||
struct target_stat64 {
|
||||
unsigned short st_dev;
|
||||
unsigned char __pad0[10];
|
||||
uint32_t __st_ino;
|
||||
unsigned int st_mode;
|
||||
unsigned int st_nlink;
|
||||
uint32_t st_uid;
|
||||
uint32_t st_gid;
|
||||
unsigned short st_rdev;
|
||||
unsigned char __pad3[10];
|
||||
unsigned char __pad31[4];
|
||||
long long st_size;
|
||||
uint32_t st_blksize;
|
||||
unsigned char __pad32[4];
|
||||
uint32_t st_blocks;
|
||||
uint32_t __pad4;
|
||||
uint32_t st32_atime;
|
||||
uint32_t __pad5;
|
||||
uint32_t st32_mtime;
|
||||
uint32_t __pad6;
|
||||
uint32_t st32_ctime;
|
||||
uint32_t __pad7;
|
||||
unsigned long long st_ino;
|
||||
};// __attribute__((packed));
|
||||
|
||||
struct target_tms32 {
|
||||
uint32_t tms_utime;
|
||||
uint32_t tms_stime;
|
||||
uint32_t tms_cutime;
|
||||
uint32_t tms_cstime;
|
||||
};
|
||||
|
||||
struct target_timeval32 {
|
||||
uint32_t tv_sec; /* seconds */
|
||||
uint32_t tv_usec; /* microseconds */
|
||||
};
|
||||
|
||||
struct target_timezone32 {
|
||||
int32_t tz_minuteswest; /* minutes west of Greenwich */
|
||||
int32_t tz_dsttime; /* type of DST correction */
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,31 +0,0 @@
|
|||
/*
|
||||
skyeye_types.h - some data types definition for skyeye debugger
|
||||
Copyright (C) 2003 Skyeye Develop Group
|
||||
for help please send mail to <skyeye-developer@lists.sf.linuxforum.net>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
*/
|
||||
/*
|
||||
* 12/16/2006 Michael.Kang <blackfin.kang@gmail.com>
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
typedef uint32_t address_t;
|
||||
typedef uint32_t physical_address_t;
|
||||
typedef uint32_t generic_address_t;
|
||||
|
|
@ -5,6 +5,8 @@
|
|||
* First, the standard VFP set.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define FPSID cr0
|
||||
#define FPSCR cr1
|
||||
#define MVFR1 cr6
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@
|
|||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __VFP_H__
|
||||
#define __VFP_H__
|
||||
#pragma once
|
||||
|
||||
#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
|
||||
|
||||
|
|
@ -109,5 +108,3 @@ int VLDR(ARMul_State * state, int type, ARMword instr, ARMword value);
|
|||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,8 +30,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __VFP_HELPER_H__
|
||||
#define __VFP_HELPER_H__
|
||||
#pragma once
|
||||
|
||||
/* Custom edit */
|
||||
|
||||
|
|
@ -536,5 +535,3 @@ u32 vfp_double_normaliseroundintern(ARMul_State* state, struct vfp_double *vd, u
|
|||
u32 vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr);
|
||||
u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn, struct vfp_double *vdm, u32 fpscr);
|
||||
u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double* dm, u32 fpscr);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue