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Merge pull request #1028 from aroulin/arm-disas-media-instr
arm_disasm: ARMv6 media instructions
This commit is contained in:
bunnei
commit
df25b047f8
2 changed files with 545 additions and 1 deletions
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@ -1,6 +1,7 @@
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// Copyright 2006 The Android Open Source Project
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#include <string>
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#include <unordered_set>
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#include "common/string_util.h"
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#include "core/arm/disassembler/arm_disasm.h"
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@ -66,13 +67,47 @@ static const char *opcode_names[] = {
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"mvn",
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"nop",
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"orr",
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"pkh",
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"pld",
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"qadd16",
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"qadd8",
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"qasx",
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"qsax",
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"qsub16",
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"qsub8",
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"rev",
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"rev16",
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"revsh",
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"rsb",
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"rsc",
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"sadd16",
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"sadd8",
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"sasx",
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"sbc",
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"sel",
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"sev",
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"shadd16",
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"shadd8",
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"shasx",
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"shsax",
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"shsub16",
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"shsub8",
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"smlad",
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"smlal",
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"smlald",
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"smlsd",
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"smlsld",
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"smmla",
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"smmls",
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"smmul",
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"smuad",
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"smull",
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"smusd",
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"ssat",
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"ssat16",
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"ssax",
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"ssub16",
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"ssub8",
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"stc",
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"stm",
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"str",
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@ -88,10 +123,44 @@ static const char *opcode_names[] = {
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"swi",
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"swp",
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"swpb",
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"sxtab",
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"sxtab16",
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"sxtah",
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"sxtb",
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"sxtb16",
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"sxth",
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"teq",
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"tst",
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"uadd16",
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"uadd8",
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"uasx",
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"uhadd16",
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"uhadd8",
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"uhasx",
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"uhsax",
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"uhsub16",
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"uhsub8",
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"umlal",
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"umull",
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"uqadd16",
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"uqadd8",
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"uqasx",
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"uqsax",
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"uqsub16",
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"uqsub8",
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"usad8",
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"usada8",
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"usat",
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"usat16",
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"usax",
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"usub16",
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"usub8",
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"uxtab",
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"uxtab16",
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"uxtah",
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"uxtb",
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"uxtb16",
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"uxth",
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"wfe",
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"wfi",
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"yield",
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@ -236,8 +305,70 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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case OP_WFI:
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case OP_YIELD:
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return DisassembleNoOperands(opcode, insn);
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case OP_PKH:
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return DisassemblePKH(insn);
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case OP_PLD:
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return DisassemblePLD(insn);
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case OP_QADD16:
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case OP_QADD8:
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case OP_QASX:
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case OP_QSAX:
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case OP_QSUB16:
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case OP_QSUB8:
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case OP_SADD16:
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case OP_SADD8:
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case OP_SASX:
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case OP_SHADD16:
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case OP_SHADD8:
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case OP_SHASX:
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case OP_SHSAX:
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case OP_SHSUB16:
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case OP_SHSUB8:
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case OP_SSAX:
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case OP_SSUB16:
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case OP_SSUB8:
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case OP_UADD16:
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case OP_UADD8:
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case OP_UASX:
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case OP_UHADD16:
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case OP_UHADD8:
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case OP_UHASX:
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case OP_UHSAX:
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case OP_UHSUB16:
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case OP_UHSUB8:
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case OP_UQADD16:
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case OP_UQADD8:
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case OP_UQASX:
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case OP_UQSAX:
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case OP_UQSUB16:
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case OP_UQSUB8:
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case OP_USAX:
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case OP_USUB16:
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case OP_USUB8:
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return DisassembleParallelAddSub(opcode, insn);
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case OP_REV:
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case OP_REV16:
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case OP_REVSH:
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return DisassembleREV(opcode, insn);
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case OP_SEL:
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return DisassembleSEL(insn);
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case OP_SMLAD:
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case OP_SMLALD:
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case OP_SMLSD:
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case OP_SMLSLD:
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case OP_SMMLA:
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case OP_SMMLS:
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case OP_SMMUL:
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case OP_SMUAD:
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case OP_SMUSD:
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case OP_USAD8:
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case OP_USADA8:
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return DisassembleMediaMulDiv(opcode, insn);
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case OP_SSAT:
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case OP_SSAT16:
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case OP_USAT:
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case OP_USAT16:
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return DisassembleSAT(opcode, insn);
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case OP_STC:
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return "stc";
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case OP_SWI:
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@ -245,6 +376,19 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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case OP_SWP:
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case OP_SWPB:
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return DisassembleSWP(opcode, insn);
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case OP_SXTAB:
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case OP_SXTAB16:
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case OP_SXTAH:
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case OP_SXTB:
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case OP_SXTB16:
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case OP_SXTH:
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case OP_UXTAB:
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case OP_UXTAB16:
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case OP_UXTAH:
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case OP_UXTB:
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case OP_UXTB16:
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case OP_UXTH:
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return DisassembleXT(opcode, insn);
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case OP_UMLAL:
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case OP_UMULL:
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case OP_SMLAL:
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@ -382,6 +526,38 @@ std::string ARM_Disasm::DisassembleCLZ(uint32_t insn)
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return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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}
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std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rd = BITS(insn, 16, 19);
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uint32_t ra = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 8, 11);
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uint32_t m = BIT(insn, 5);
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uint32_t rn = BITS(insn, 0, 3);
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std::string cross = "";
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if (m) {
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if (opcode == OP_SMMLA || opcode == OP_SMMUL || opcode == OP_SMMLS)
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cross = "r";
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else
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cross = "x";
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}
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std::string ext_reg = "";
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std::unordered_set<Opcode, std::hash<int>> with_ext_reg = {
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OP_SMLAD, OP_SMLSD, OP_SMMLA, OP_SMMLS, OP_USADA8
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};
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if (with_ext_reg.find(opcode) != with_ext_reg.end())
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ext_reg = Common::StringFromFormat(", r%u", ra);
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std::string rd_low = "";
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if (opcode == OP_SMLALD || opcode == OP_SMLSLD)
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rd_low = Common::StringFromFormat("r%u, ", ra);
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return Common::StringFromFormat("%s%s%s\t%sr%u, r%u, r%u%s", opcode_names[opcode],
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cross.c_str(), cond_to_str(cond), rd_low.c_str(), rd, rn, rm,
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ext_reg.c_str());
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}
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std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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{
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std::string tmp_list;
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@ -684,6 +860,40 @@ std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, uint32_t insn)
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return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
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}
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std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 0, 3);
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return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[opcode], cond_to_str(cond),
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rd, rn, rm);
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}
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std::string ARM_Disasm::DisassemblePKH(uint32_t insn)
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{
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t imm5 = BITS(insn, 7, 11);
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uint32_t tb = BIT(insn, 6);
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uint32_t rm = BITS(insn, 0, 3);
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std::string suffix = tb ? "tb" : "bt";
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std::string shift = "";
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if (tb && imm5 == 0)
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imm5 = 32;
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if (imm5 > 0) {
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shift = tb ? ", ASR" : ", LSL";
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shift += " #" + std::to_string(imm5);
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}
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return Common::StringFromFormat("pkh%s%s\tr%u, r%u, r%u%s", suffix.c_str(), cond_to_str(cond),
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rd, rn, rm, shift.c_str());
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}
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std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
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{
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uint8_t is_reg = (insn >> 25) & 0x1;
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@ -707,6 +917,15 @@ std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
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}
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}
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std::string ARM_Disasm::DisassembleREV(Opcode opcode, uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 0, 3);
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return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond),
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rd, rm);
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}
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std::string ARM_Disasm::DisassembleREX(Opcode opcode, uint32_t insn) {
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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@ -737,6 +956,44 @@ std::string ARM_Disasm::DisassembleREX(Opcode opcode, uint32_t insn) {
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}
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}
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std::string ARM_Disasm::DisassembleSAT(Opcode opcode, uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t sat_imm = BITS(insn, 16, 20);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t imm5 = BITS(insn, 7, 11);
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uint32_t sh = BIT(insn, 6);
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uint32_t rn = BITS(insn, 0, 3);
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std::string shift_part = "";
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bool opcode_has_shift = (opcode == OP_SSAT) || (opcode == OP_USAT);
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if (opcode_has_shift && !(sh == 0 && imm5 == 0)) {
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if (sh == 0)
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shift_part += ", LSL #";
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else
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shift_part += ", ASR #";
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if (imm5 == 0)
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imm5 = 32;
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shift_part += std::to_string(imm5);
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}
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if (opcode == OP_SSAT || opcode == OP_SSAT16)
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sat_imm++;
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return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode], cond_to_str(cond), rd,
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sat_imm, rn, shift_part.c_str());
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}
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std::string ARM_Disasm::DisassembleSEL(uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 0, 3);
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return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[OP_SEL], cond_to_str(cond),
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rd, rn, rm);
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}
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std::string ARM_Disasm::DisassembleSWI(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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@ -756,6 +1013,30 @@ std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn)
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return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
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}
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std::string ARM_Disasm::DisassembleXT(Opcode opcode, uint32_t insn)
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{
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rotate = BITS(insn, 10, 11);
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uint32_t rm = BITS(insn, 0, 3);
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std::string rn_part = "";
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static std::unordered_set<Opcode, std::hash<int>> extend_with_add = {
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OP_SXTAB, OP_SXTAB16, OP_SXTAH,
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OP_UXTAB, OP_UXTAB16, OP_UXTAH
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};
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if (extend_with_add.find(opcode) != extend_with_add.end())
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rn_part = ", r" + std::to_string(rn);
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std::string rotate_part = "";
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if (rotate != 0)
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rotate_part = ", ROR #" + std::to_string(rotate << 3);
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return Common::StringFromFormat("%s%s\tr%u%s, r%u%s", opcode_names[opcode], cond_to_str(cond),
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rd, rn_part.c_str(), rm, rotate_part.c_str());
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}
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Opcode ARM_Disasm::Decode(uint32_t insn) {
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uint32_t bits27_26 = (insn >> 26) & 0x3;
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switch (bits27_26) {
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@ -818,7 +1099,7 @@ Opcode ARM_Disasm::Decode01(uint32_t insn) {
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uint8_t is_reg = (insn >> 25) & 0x1;
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uint8_t bit4 = (insn >> 4) & 0x1;
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if (is_reg == 1 && bit4 == 1)
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return OP_UNDEFINED;
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return DecodeMedia(insn);
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t is_byte = (insn >> 22) & 0x1;
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if ((insn & 0xfd70f000) == 0xf550f000) {
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|
@ -940,6 +1221,120 @@ Opcode ARM_Disasm::DecodeSyncPrimitive(uint32_t insn) {
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}
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}
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Opcode ARM_Disasm::DecodeParallelAddSub(uint32_t insn) {
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uint32_t op1 = BITS(insn, 20, 21);
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uint32_t op2 = BITS(insn, 5, 7);
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uint32_t is_unsigned = BIT(insn, 22);
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if (op1 == 0x0 || op2 == 0x5 || op2 == 0x6)
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return OP_UNDEFINED;
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// change op1 range from [1, 3] to range [0, 2]
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op1--;
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// change op2 range from [0, 4] U {7} to range [0, 5]
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if (op2 == 0x7)
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op2 = 0x5;
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static std::vector<Opcode> opcodes = {
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// op1 = 0
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OP_SADD16, OP_UADD16,
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OP_SASX, OP_UASX,
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OP_SSAX, OP_USAX,
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OP_SSUB16, OP_USUB16,
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OP_SADD8, OP_UADD8,
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OP_SSUB8, OP_USUB8,
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// op1 = 1
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OP_QADD16, OP_UQADD16,
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OP_QASX, OP_UQASX,
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OP_QSAX, OP_UQSAX,
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OP_QSUB16, OP_UQSUB16,
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OP_QADD8, OP_UQADD8,
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OP_QSUB8, OP_UQSUB8,
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// op1 = 2
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OP_SHADD16, OP_UHADD16,
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OP_SHASX, OP_UHASX,
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OP_SHSAX, OP_UHSAX,
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OP_SHSUB16, OP_UHSUB16,
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OP_SHADD8, OP_UHADD8,
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OP_SHSUB8, OP_UHSUB8
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};
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uint32_t opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
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return opcodes[opcode_index];
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}
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Opcode ARM_Disasm::DecodePackingSaturationReversal(uint32_t insn) {
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uint32_t op1 = BITS(insn, 20, 22);
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uint32_t a = BITS(insn, 16, 19);
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uint32_t op2 = BITS(insn, 5, 7);
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switch (op1) {
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case 0x0:
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if (BIT(op2, 0) == 0)
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return OP_PKH;
|
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if (op2 == 0x3 && a != 0xf)
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return OP_SXTAB16;
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if (op2 == 0x3 && a == 0xf)
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return OP_SXTB16;
|
||||
if (op2 == 0x5)
|
||||
return OP_SEL;
|
||||
break;
|
||||
case 0x2:
|
||||
if (BIT(op2, 0) == 0)
|
||||
return OP_SSAT;
|
||||
if (op2 == 0x1)
|
||||
return OP_SSAT16;
|
||||
if (op2 == 0x3 && a != 0xf)
|
||||
return OP_SXTAB;
|
||||
if (op2 == 0x3 && a == 0xf)
|
||||
return OP_SXTB;
|
||||
break;
|
||||
case 0x3:
|
||||
if (op2 == 0x1)
|
||||
return OP_REV;
|
||||
if (BIT(op2, 0) == 0)
|
||||
return OP_SSAT;
|
||||
if (op2 == 0x3 && a != 0xf)
|
||||
return OP_SXTAH;
|
||||
if (op2 == 0x3 && a == 0xf)
|
||||
return OP_SXTH;
|
||||
if (op2 == 0x5)
|
||||
return OP_REV16;
|
||||
break;
|
||||
case 0x4:
|
||||
if (op2 == 0x3 && a != 0xf)
|
||||
return OP_UXTAB16;
|
||||
if (op2 == 0x3 && a == 0xf)
|
||||
return OP_UXTB16;
|
||||
break;
|
||||
case 0x6:
|
||||
if (BIT(op2, 0) == 0)
|
||||
return OP_USAT;
|
||||
if (op2 == 0x1)
|
||||
return OP_USAT16;
|
||||
if (op2 == 0x3 && a != 0xf)
|
||||
return OP_UXTAB;
|
||||
if (op2 == 0x3 && a == 0xf)
|
||||
return OP_UXTB;
|
||||
break;
|
||||
case 0x7:
|
||||
if (BIT(op2, 0) == 0)
|
||||
return OP_USAT;
|
||||
if (op2 == 0x3 && a != 0xf)
|
||||
return OP_UXTAH;
|
||||
if (op2 == 0x3 && a == 0xf)
|
||||
return OP_UXTH;
|
||||
if (op2 == 0x5)
|
||||
return OP_REVSH;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return OP_UNDEFINED;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
|
||||
uint8_t bit24 = (insn >> 24) & 0x1;
|
||||
if (bit24 != 0) {
|
||||
|
|
@ -999,6 +1394,76 @@ Opcode ARM_Disasm::DecodeMSRImmAndHints(uint32_t insn) {
|
|||
return OP_MSR;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeMediaMulDiv(uint32_t insn) {
|
||||
uint32_t op1 = BITS(insn, 20, 22);
|
||||
uint32_t op2_h = BITS(insn, 6, 7);
|
||||
uint32_t a = BITS(insn, 12, 15);
|
||||
|
||||
switch (op1) {
|
||||
case 0x0:
|
||||
if (op2_h == 0x0) {
|
||||
if (a != 0xf)
|
||||
return OP_SMLAD;
|
||||
else
|
||||
return OP_SMUAD;
|
||||
} else if (op2_h == 0x1) {
|
||||
if (a != 0xf)
|
||||
return OP_SMLSD;
|
||||
else
|
||||
return OP_SMUSD;
|
||||
}
|
||||
break;
|
||||
case 0x4:
|
||||
if (op2_h == 0x0)
|
||||
return OP_SMLALD;
|
||||
else if (op2_h == 0x1)
|
||||
return OP_SMLSLD;
|
||||
break;
|
||||
case 0x5:
|
||||
if (op2_h == 0x0) {
|
||||
if (a != 0xf)
|
||||
return OP_SMMLA;
|
||||
else
|
||||
return OP_SMMUL;
|
||||
} else if (op2_h == 0x3) {
|
||||
return OP_SMMLS;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return OP_UNDEFINED;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeMedia(uint32_t insn) {
|
||||
uint32_t op1 = BITS(insn, 20, 24);
|
||||
uint32_t rd = BITS(insn, 12, 15);
|
||||
uint32_t op2 = BITS(insn, 5, 7);
|
||||
|
||||
switch (BITS(op1, 3, 4)) {
|
||||
case 0x0:
|
||||
// unsigned and signed parallel addition and subtraction
|
||||
return DecodeParallelAddSub(insn);
|
||||
case 0x1:
|
||||
// Packing, unpacking, saturation, and reversal
|
||||
return DecodePackingSaturationReversal(insn);
|
||||
case 0x2:
|
||||
// Signed multiply, signed and unsigned divide
|
||||
return DecodeMediaMulDiv(insn);
|
||||
case 0x3:
|
||||
if (op2 == 0 && rd == 0xf)
|
||||
return OP_USAD8;
|
||||
if (op2 == 0 && rd != 0xf)
|
||||
return OP_USADA8;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return OP_UNDEFINED;
|
||||
}
|
||||
|
||||
Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
|
||||
uint8_t is_load = (insn >> 20) & 0x1;
|
||||
uint8_t bits_65 = (insn >> 5) & 0x3;
|
||||
|
|
|
|||
|
|
@ -48,13 +48,47 @@ enum Opcode {
|
|||
OP_MVN,
|
||||
OP_NOP,
|
||||
OP_ORR,
|
||||
OP_PKH,
|
||||
OP_PLD,
|
||||
OP_QADD16,
|
||||
OP_QADD8,
|
||||
OP_QASX,
|
||||
OP_QSAX,
|
||||
OP_QSUB16,
|
||||
OP_QSUB8,
|
||||
OP_REV,
|
||||
OP_REV16,
|
||||
OP_REVSH,
|
||||
OP_RSB,
|
||||
OP_RSC,
|
||||
OP_SADD16,
|
||||
OP_SADD8,
|
||||
OP_SASX,
|
||||
OP_SBC,
|
||||
OP_SEL,
|
||||
OP_SEV,
|
||||
OP_SHADD16,
|
||||
OP_SHADD8,
|
||||
OP_SHASX,
|
||||
OP_SHSAX,
|
||||
OP_SHSUB16,
|
||||
OP_SHSUB8,
|
||||
OP_SMLAD,
|
||||
OP_SMLAL,
|
||||
OP_SMLALD,
|
||||
OP_SMLSD,
|
||||
OP_SMLSLD,
|
||||
OP_SMMLA,
|
||||
OP_SMMLS,
|
||||
OP_SMMUL,
|
||||
OP_SMUAD,
|
||||
OP_SMULL,
|
||||
OP_SMUSD,
|
||||
OP_SSAT,
|
||||
OP_SSAT16,
|
||||
OP_SSAX,
|
||||
OP_SSUB16,
|
||||
OP_SSUB8,
|
||||
OP_STC,
|
||||
OP_STM,
|
||||
OP_STR,
|
||||
|
|
@ -70,10 +104,44 @@ enum Opcode {
|
|||
OP_SWI,
|
||||
OP_SWP,
|
||||
OP_SWPB,
|
||||
OP_SXTAB,
|
||||
OP_SXTAB16,
|
||||
OP_SXTAH,
|
||||
OP_SXTB,
|
||||
OP_SXTB16,
|
||||
OP_SXTH,
|
||||
OP_TEQ,
|
||||
OP_TST,
|
||||
OP_UADD16,
|
||||
OP_UADD8,
|
||||
OP_UASX,
|
||||
OP_UHADD16,
|
||||
OP_UHADD8,
|
||||
OP_UHASX,
|
||||
OP_UHSAX,
|
||||
OP_UHSUB16,
|
||||
OP_UHSUB8,
|
||||
OP_UMLAL,
|
||||
OP_UMULL,
|
||||
OP_UQADD16,
|
||||
OP_UQADD8,
|
||||
OP_UQASX,
|
||||
OP_UQSAX,
|
||||
OP_UQSUB16,
|
||||
OP_UQSUB8,
|
||||
OP_USAD8,
|
||||
OP_USADA8,
|
||||
OP_USAT,
|
||||
OP_USAT16,
|
||||
OP_USAX,
|
||||
OP_USUB16,
|
||||
OP_USUB8,
|
||||
OP_UXTAB,
|
||||
OP_UXTAB16,
|
||||
OP_UXTAH,
|
||||
OP_UXTB,
|
||||
OP_UXTB16,
|
||||
OP_UXTH,
|
||||
OP_WFE,
|
||||
OP_WFI,
|
||||
OP_YIELD,
|
||||
|
|
@ -132,8 +200,12 @@ class ARM_Disasm {
|
|||
static Opcode Decode10(uint32_t insn);
|
||||
static Opcode Decode11(uint32_t insn);
|
||||
static Opcode DecodeSyncPrimitive(uint32_t insn);
|
||||
static Opcode DecodeParallelAddSub(uint32_t insn);
|
||||
static Opcode DecodePackingSaturationReversal(uint32_t insn);
|
||||
static Opcode DecodeMUL(uint32_t insn);
|
||||
static Opcode DecodeMSRImmAndHints(uint32_t insn);
|
||||
static Opcode DecodeMediaMulDiv(uint32_t insn);
|
||||
static Opcode DecodeMedia(uint32_t insn);
|
||||
static Opcode DecodeLDRH(uint32_t insn);
|
||||
static Opcode DecodeALU(uint32_t insn);
|
||||
|
||||
|
|
@ -142,6 +214,7 @@ class ARM_Disasm {
|
|||
static std::string DisassembleBX(uint32_t insn);
|
||||
static std::string DisassembleBKPT(uint32_t insn);
|
||||
static std::string DisassembleCLZ(uint32_t insn);
|
||||
static std::string DisassembleMediaMulDiv(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMemblock(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleMem(uint32_t insn);
|
||||
static std::string DisassembleMemHalf(uint32_t insn);
|
||||
|
|
@ -152,8 +225,14 @@ class ARM_Disasm {
|
|||
static std::string DisassembleMRS(uint32_t insn);
|
||||
static std::string DisassembleMSR(uint32_t insn);
|
||||
static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleParallelAddSub(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassemblePKH(uint32_t insn);
|
||||
static std::string DisassemblePLD(uint32_t insn);
|
||||
static std::string DisassembleREV(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleREX(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleSAT(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleSEL(uint32_t insn);
|
||||
static std::string DisassembleSWI(uint32_t insn);
|
||||
static std::string DisassembleSWP(Opcode opcode, uint32_t insn);
|
||||
static std::string DisassembleXT(Opcode opcode, uint32_t insn);
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue