N-archive/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-23 15:22:45 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

Shaders/TEXS: Fixed the component mask in the TEXS instruction.

Browse source 
Previously we could end up with a TEXS that didn't write any outputs, this was wrong.
This commit is contained in:
Subv 2018-08-19 14:00:12 -05:00
parent 29d4f8c2dd
commit f7edbcd7a3
1 changed files with 11 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
src/video_core/engines/shader_bytecode.h
View file

@ -12,6 +12,7 @@
#include <boost/optional.hpp> #include <boost/optional.hpp>
#include "common/assert.h"
#include "common/bit_field.h" #include "common/bit_field.h"
#include "common/common_types.h" #include "common/common_types.h"
@ -446,16 +447,20 @@ union Instruction {
} }
bool IsComponentEnabled(size_t component) const { bool IsComponentEnabled(size_t component) const {
static constexpr std::array<std::array<u32, 8>, 4> mask_lut{ static constexpr std::array<std::array<u32, 8>, 4> mask_lut{{
{{}, {},
{0x1, 0x2, 0x4, 0x8, 0x3}, {0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc},
{0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc}, {0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc},
{0x7, 0xb, 0xd, 0xe, 0xf}}}; {0x7, 0xb, 0xd, 0xe, 0xf},
}};
size_t index{gpr0.Value() != Register::ZeroIndex ? 1U : 0U}; size_t index{gpr0.Value() != Register::ZeroIndex ? 1U : 0U};
index |= gpr28.Value() != Register::ZeroIndex ? 2 : 0; index |= gpr28.Value() != Register::ZeroIndex ? 2 : 0;
return ((1ull << component) & mask_lut[index][component_mask_selector]) != 0; u32 mask = mask_lut[index][component_mask_selector];
// A mask of 0 means this instruction uses an unimplemented mask.
ASSERT(mask != 0);
return ((1ull << component) & mask) != 0;
} }
} texs; } texs;