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710 commits

Author SHA1 Message Date
ReinUsesLisp
238c6016f9 maxwell_3d: Initialize format attributes constant as one 
nouveau expects this to be true but it doesn't set it.
 2020-04-16 21:15:07 -03:00
Fernando Sahmkow
e33196d4e7
Merge pull request #3612 from ReinUsesLisp/red 
shader/memory: Implement RED.E.ADD and minor changes to ATOM
 2020-04-15 15:03:49 -04:00
Mat M
64b5985f0a
Merge pull request #3662 from ReinUsesLisp/constant-attrs 
gl_rasterizer: Implement constant vertex attributes
 2020-04-15 11:54:50 -04:00
ReinUsesLisp
fefe7f18f9 shader/arithmetic: Add FCMP_CR variant 
Adds another variant of FCMP.
 2020-04-14 19:11:04 -03:00
ReinUsesLisp
6dfcabc800 gl_rasterizer: Implement constant vertex attributes 
Credits go to gdkchan from Ryujinx for finding constant attributes are
used in retail games.
 2020-04-14 17:58:53 -03:00
ReinUsesLisp
76615b9f34 gl_rasterizer: Implement line widths and smooth lines 
Implements "legacy" features from OpenGL present on hardware such as
smooth lines and line width.
 2020-04-13 01:30:34 -03:00
Fernando Sahmkow
3d91dbb21d
Merge pull request #3578 from ReinUsesLisp/vmnmx 
shader/video: Partially implement VMNMX
 2020-04-12 10:44:03 -04:00
ReinUsesLisp
76f178ba6e shader/video: Partially implement VMNMX 
Implements the common usages for VMNMX. Inputs with a different size
than 32 bits are not supported and sign mismatches aren't supported
either.

VMNMX works as follows:
It grabs Ra and Rb and applies a maximum/minimum on them (this is
defined by .MX), having in mind the input sign. This result can then be
saturated. After the intermediate result is calculated, it applies
another operation on it using Rc. These operations are merges,
accumulations or another min/max pass.

This instruction allows to implement with a more flexible approach GCN's
min3 and max3 instructions (for instance).
 2020-04-12 00:34:42 -03:00
ReinUsesLisp
a7baf6fee4 video_core: Add MSAA registers in 3D engine and TIC 
This adds the registers used for multisampling. It doesn't implement
anything for now.
 2020-04-12 00:21:27 -03:00
bunnei
b96fd0bd0e
Merge pull request #3601 from ReinUsesLisp/some-shader-encodings 
video_core/shader: Add some instruction and S2R encodings
 2020-04-09 00:17:39 -04:00
ReinUsesLisp
3185245845 shader/memory: Implement RED.E.ADD 
Implements a reduction operation. It's an atomic operation that doesn't
return a value.

This commit introduces another primitive because some shading languages
might have a primitive for reduction operations.
 2020-04-06 02:24:47 -03:00
ReinUsesLisp
8b719e9e1d shader_bytecode: Rename MOV_SYS to S2R 2020-04-04 03:37:51 -03:00
ReinUsesLisp
9d15feb892 shader_bytecode: Add encoding for BAR 2020-04-04 03:36:21 -03:00
ReinUsesLisp
c02a2dc24a shader_bytecode: Add encoding for VOTE.VTG 2020-04-04 03:28:11 -03:00
ReinUsesLisp
2339fe199f shader_decompiler: Remove FragCoord.w hack and change IPA implementation 
Credits go to gdkchan and Ryujinx. The pull request used for this can
be found here: https://github.com/Ryujinx/Ryujinx/pull/1082

yuzu was already using the header for interpolation, but it was missing
the FragCoord.w multiplication described in the linked pull request.
This commit finally removes the FragCoord.w == 1.0f hack from the shader
decompiler.

While we are at it, this commit renames some enumerations to match
Nvidia's documentation (linked below) and fixes component declaration
order in the shader program header (z and w were swapped).

https://github.com/NVIDIA/open-gpu-doc/blob/master/Shader-Program-Header/Shader-Program-Header.html
 2020-04-01 21:48:55 -03:00
namkazy
c8f6d9effd shader_decode: merge GlobalAtomicOp to AtomicOp 2020-03-30 18:47:00 +07:00
ReinUsesLisp
08470d261d shader_bytecode: Fix I2I_IMM encoding 2020-03-28 18:49:07 -03:00
ReinUsesLisp
cedbe925cd engines/const_buffer_engine_interface: Store image format type 
This information is required to properly implement SULD.B. It might also
be handy for all image operations, since it would allow us to implement
them on devices that require the image format to be specified (on
desktop, this would be AMD on OpenGL and Intel on OpenGL and Vulkan).
 2020-03-27 00:36:22 -03:00
bunnei
e6aff11057
Merge pull request #3520 from ReinUsesLisp/legacy-varyings 
gl_shader_decompiler: Implement legacy varyings
 2020-03-25 19:27:51 -04:00
namkazy
fc37672f26 apply replay logic to all writes. remove replay from MacroInterpreter::Send (@fincs) 2020-03-22 22:25:44 +07:00
namkazy
f66743cd0c maxwell_3d: change declaration order 2020-03-22 13:41:16 +07:00
namkazy
d4e93cf38c maxwell_3d: init shadow_state 2020-03-22 13:35:11 +07:00
namkazy
22f4268c2f maxwell_3d: this seem more correct. 2020-03-22 12:02:54 +07:00
namkazy
7051dc1902 maxwell_3d: update comments for shadow ram usage 2020-03-22 11:35:26 +07:00
Nguyen Dac Nam
63c2635e6f maxwell_3d: track shadow ram ctrl and hw reg value 2020-03-22 10:53:41 +07:00
Nguyen Dac Nam
dbfbe352e0 maxwell_3d: implement MME shadow RAM 2020-03-22 10:53:35 +07:00
ReinUsesLisp
9f46066bda kepler_compute: Remove unused variables 2020-03-18 20:03:19 -03:00
Rodrigo Locatti
ddafc99776
Merge pull request #3502 from namkazt/patch-3 
shader_decode: Reimplement BFE instructions
 2020-03-15 21:23:04 -03:00
ReinUsesLisp
6442e02c5d shader/shader_ir: Track usage in input attribute and of legacy varyings 2020-03-15 21:01:52 -03:00
ReinUsesLisp
afebdda203 maxwell_3d: Add padding words to XFB entries 
Use INSERT_UNION_PADDING_WORDS instead of alignas to ensure a size
requirement.
 2020-03-13 18:33:05 -03:00
ReinUsesLisp
8e9f23f393 gl_rasterizer: Implement transform feedback bindings 2020-03-13 18:33:04 -03:00
Rodrigo Locatti
244fe13219
Merge branch 'master' into shader-purge 2020-03-13 16:44:06 -03:00
Nguyen Dac Nam
93547cac68
shader_bytecode: update BFE instructions struct. 2020-03-13 12:52:16 +07:00
ReinUsesLisp
e4bc3c3342 gl_rasterizer: Implement polygon modes and fill rectangles 2020-03-09 20:39:58 -03:00
ReinUsesLisp
eb5861e0a2 engines/maxwell_3d: Add TFB registers and store them in shader registry 2020-03-09 18:40:53 -03:00
ReinUsesLisp
978172530e const_buffer_engine_interface: Store component types 
This is required for Vulkan. Sampling integer textures with float
handles is illegal.
 2020-03-09 18:40:53 -03:00
ReinUsesLisp
042256c6bb state_tracker: Remove type traits with named structures 2020-02-28 17:56:43 -03:00
ReinUsesLisp
15cadc3948 maxwell_3d: Use two tables instead of three for dirty flags 2020-02-28 17:56:42 -03:00
ReinUsesLisp
9b08698a0c maxwell_3d: Change write dirty flags to a bitset 2020-02-28 17:56:42 -03:00
ReinUsesLisp
9e74e6988b maxwell_3d: Flatten cull and front face registers 2020-02-28 17:56:41 -03:00
ReinUsesLisp
eed789d0d1 video_core: Reintroduce dirty flags infrastructure 2020-02-28 17:56:41 -03:00
ReinUsesLisp
1eee891f6e gl_state: Remove clip distances tracking 2020-02-28 17:26:26 -03:00
ReinUsesLisp
d3e433a380 gl_state: Remove viewport and depth range tracking 2020-02-28 17:25:18 -03:00
ReinUsesLisp
96ac3d518a gl_rasterizer: Remove dirty flags 2020-02-28 16:39:27 -03:00
bunnei
e22ad52cdb
Merge pull request #3425 from ReinUsesLisp/layered-framebuffer 
texture_cache: Implement layered framebuffer attachments
 2020-02-24 10:14:50 -05:00
bunnei
b2bc7682b4
Merge pull request #3414 from ReinUsesLisp/maxwell-3d-draw 
maxwell_3d: Unify draw methods
 2020-02-19 16:13:50 -05:00
Fernando Sahmkow
93acfbd3a5
Merge pull request #3409 from ReinUsesLisp/host-queries 
query_cache: Implement a query cache and query 21 (samples passed)
 2020-02-18 11:31:06 -04:00
ReinUsesLisp
6a0220b2e1 texture_cache: Implement layered framebuffer attachments 
Layered framebuffer attachments is a feature that allows applications to
write attach layered textures to a single attachment. What layer the
fragments are written to is decided from the shader using gl_Layer.
 2020-02-16 04:19:32 -03:00
ReinUsesLisp
91aa58e410 maxwell_3d: Unify draw methods 
Pass instanced state of a draw invocation as an argument instead of
having two separate virtual methods.
 2020-02-14 18:09:40 -03:00
ReinUsesLisp
73d2d3342d gl_query_cache: Optimize query cache 
Use a custom cache instead of relying on a ranged cache.
 2020-02-14 17:38:27 -03:00