Commit graph

226 commits

Author SHA1 Message Date
lat9nq
eebf39b3c0 arm_dynarmic_64: Re-add fastmem_address_space_bits to Auto setting 2021-07-08 15:14:45 -04:00
lat9nq
87b6e14d7c arm_dynarmic{32,64}: Fixes from test build
Now sets optimizations regardless of the Settings. Drops unsafe fastmem
optimization.
2021-07-08 14:56:09 -04:00
lat9nq
7ab5767157 core,common,yuzu qt: Add CPU accuracy option 'Auto'
The current CPU accuracy settings in yuzu are fairly polarized and
require more than common knowledge to know what the optimal settings for
yuzu would be. This adds a curated option called 'Auto' that applies a
few at the moment known-good unsafe optimizations to Dynarmic.
2021-07-08 14:56:09 -04:00
Wunkolo
4569f39c7c common: Replace common_sizes into user-literals
Removes common_sizes.h in favor of having `_KiB`, `_MiB`, `_GiB`, etc
user-literals within literals.h.

To keep the global namespace clean, users will have to use:

```
using namespace Common::Literals;
```

to access these literals.
2021-06-24 09:27:40 -07:00
Fernando Sahmkow
2298508465 Update dynarmic and add new unsafe CPU option. 2021-06-20 20:40:02 +02:00
FernandoS27
5ba28325b2 General: Add settings for fastmem and disabling adress space check. 2021-06-11 17:27:17 +02:00
Markus Wick
621f3f5f47 core: Make use of fastmem 2021-06-11 17:27:06 +02:00
bunnei
f34176996e
Merge pull request #6385 from degasus/save_memory_access
core/memory: Check our memory fallbacks for out-of-bound behavior.
2021-05-30 23:21:39 -07:00
Markus Wick
ddb186e61d core/arm_interface: Improve the performance of memory fallbacks.
We just create one memory subsystem. This is a constant all the time.
So there is no need to call the non-inlined parent.Memory() helper on every callback.
2021-05-29 09:02:19 +02:00
Markus Wick
d2d7a5060f externals: Update dynarmic.
The new version supports fastmem on a64.
2021-05-29 08:53:01 +02:00
Markus Wick
3d2e80daed core/arm_interface: Call SVC after end of dynarmic block.
So we can modify all of dynarmic states within SVC without ExceptionalExit.

Especially as the ExceptionalExit hack is dropped on upstream dynarmic.
2021-05-27 23:23:23 +02:00
Markus Wick
993dbe49fc core/arm: Drop ChangeProcessorID.
This code was used to switch the CPU ID on thread switches.
However since "hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.", the CPU ID is not a constant.
This has been dead code since this rewrite, and dropped in dynarmic as well. So there is no need to keep it.
2021-05-26 19:48:24 +02:00
bunnei
7626ca3343
Merge pull request #6321 from lat9nq/per-game-cpu
configuration: Add CPU tab to game properties and slight per-game settings rework
2021-05-20 20:10:56 -07:00
Lioncash
9a07ed53eb core: Make variable shadowing a compile-time error
Now that we have most of core free of shadowing, we can enable the
warning as an error to catch anything that may be remaining and also
eliminate this class of logic bug entirely.
2021-05-16 03:43:16 -04:00
lat9nq
e169fdad4f general: Make CPU accuracy and related a Settings::Setting
Required to make CPU accuracy and unsafe settings available to use as a
per-game setting.
2021-05-15 20:46:48 -04:00
bunnei
2a7eff57a8 hle: kernel: Rename Process to KProcess. 2021-05-05 16:40:52 -07:00
Lioncash
9e726a9250 service: Resolve cases of member field shadowing
Now all that remains is for kernel code to be 'shadow-free' and then
-Wshadow can be turned into an error.
2021-05-04 04:38:38 -04:00
Lioncash
ebb64d5bf4 core: Resolve misc cases of variable shadowing
Resolves shadowing warnings that aren't in a particularly large
subsection of core. Brings us closer to turning -Wshadow into an error.

All that remains now is for cases in the kernel (left untouched for now
since a big change by bunnei is pending), and a few left over in the
service code (will be tackled next).
2021-05-03 01:19:13 -04:00
bunnei
a4c6712a4b common: Move settings to common from core.
- Removes a dependency on core and input_common from common.
2021-04-14 16:24:03 -07:00
MerryMage
0fbd7752c3 arm_dynarmic: Increase size of code cache 2021-04-02 18:09:15 +01:00
MerryMage
52dae41d7f arm_dynarmic: Always have a 'valid' jit instance 2021-03-24 18:47:17 +00:00
bunnei
a35717b245 core: arm_dynarmic: Ensure JIT state is saved/restored on page table changes.
- We re-create the JIT here without preserving any state.
2021-03-21 15:25:25 -07:00
MerryMage
821fc4a7b6 arm_dynarmic_32: Print out CPSR.T on exception 2021-02-01 18:35:33 +00:00
bunnei
c8fe8247ee arm: dynarmic: Reintroduce JIT checks on SaveContext/LoadContext. 2021-01-28 21:50:39 -08:00
bunnei
055194d2ab core: arm: Remove unnecessary JIT checks. 2021-01-28 21:42:26 -08:00
bunnei
9a4e148f9e arm: arm_dynarmic: Skip calls when JIT is invalid.
- This can happen if called from an idle or suspension thread.
2021-01-28 21:42:25 -08:00
ReinUsesLisp
b4451c5e81 core: Silence unhandled enum in switch warnings 2021-01-08 23:21:07 -03:00
MerryMage
57c9da1b39 dynarmic: Add Unsafe_InaccurateNaN optimization 2021-01-02 20:13:21 +00:00
ReinUsesLisp
b3587102d1 core/memory: Read and write page table atomically
Squash attributes into the pointer's integer, making them an uintptr_t
pair containing 2 bits at the bottom and then the pointer. These bits
are currently unused thanks to alignment requirements.

Configure Dynarmic to mask out these bits on pointer reads.

While we are at it, remove some unused attributes carried over from
Citra.

Read/Write and other hot functions use a two step unpacking process that
is less readable to stop MSVC from emitting an extra AND instruction in
the hot path:

 mov         rdi,rcx
 shr         rdx,0Ch
 mov         r8,qword ptr [rax+8]
 mov         rax,qword ptr [r8+rdx*8]
 mov         rdx,rax
-and         al,3
 and         rdx,0FFFFFFFFFFFFFFFCh
 je          Core::Memory::Memory::Impl::Read<unsigned char>
 mov         rax,qword ptr [vaddr]
 movzx       eax,byte ptr [rdx+rax]
2020-12-29 21:54:49 -03:00
bunnei
9e29e36a78 hle: kernel: Rewrite scheduler implementation based on Mesopshere. 2020-12-06 00:03:24 -08:00
bunnei
c10a37e5b6 hle: kernel: physical_core: Clear exclusive state after each run.
- This is closer to pre-multicore behavior, and works a bit better.
2020-12-06 00:03:24 -08:00
bunnei
63fd1bb503 core: arm: Implement InvalidateCacheRange for CPU cache invalidation. 2020-11-29 01:31:52 -08:00
bunnei
7b642c7781 hle: kernel: multicore: Replace n-JITs impl. with 4 JITs. 2020-11-29 01:31:51 -08:00
Lioncash
5bc4eabe36 core: Eliminate remaining usages of the global system instance
Removes all remaining usages of the global system instance. After this,
migration can begin to migrate to being constructed and managed entirely
by the various frontends.
2020-11-27 11:40:45 -05:00
Lioncash
fc6db97a09 core: Remove usage of unicorn
Unicorn long-since lost most of its use, due to dynarmic gaining support
for handling most instructions. At this point any further issues
encountered should be used to make dynarmic better.

This also allows us to remove our dependency on Python.
2020-11-03 20:22:05 -05:00
bunnei
3d592972dc
Revert "core: Fix clang build" 2020-10-20 19:07:39 -07:00
Lioncash
be1954e04c core: Fix clang build
Recent changes to the build system that made more warnings be flagged as
errors caused building via clang to break.

Fixes #4795
2020-10-17 19:50:39 -04:00
Lioncash
ff45c39578 General: Make use of std::nullopt where applicable
Allows some implementations to avoid completely zeroing out the internal
buffer of the optional, and instead only set the validity byte within
the structure.

This also makes it consistent how we return empty optionals.
2020-09-22 17:32:33 -04:00
Lioncash
1ee9ceb5af arm_dynarmic_cp15: Initialize member variables
Ensures that the member variables are always initialized to a
deterministic value on creation.
2020-09-17 13:03:49 -04:00
MerryMage
836ec9176a dynarmic: Add unsafe optimizations 2020-08-16 14:15:39 +01:00
MerryMage
505aa3a4c1 configure_cpu: Show/Hide debugging options 2020-07-11 16:38:38 +01:00
MerryMage
0193202964 configuration: Add settings to enable/disable specific CPU optimizations 2020-07-11 14:34:09 +01:00
Fernando Sahmkow
2f8947583f Core/Common: Address Feedback. 2020-06-27 18:20:06 -04:00
Fernando Sahmkow
4105f38022 SVC: Implement 32-bits wrappers and update Dynarmic. 2020-06-27 11:36:27 -04:00
Fernando Sahmkow
b8df61c642 ARM: Update Dynarmic and Setup A32 according to latest interface. 2020-06-27 11:36:26 -04:00
Fernando Sahmkow
ec11918323 ArmDynarmic32: Setup CNTPCT correctly 2020-06-27 11:36:24 -04:00
Fernando Sahmkow
0a8013d71e ARMDynarmicInterface: Correct GCC Build Errors. 2020-06-27 11:36:17 -04:00
Fernando Sahmkow
3714f2e471 ARMInterface/Externals: Update dynarmic and fit to latest version. 2020-06-27 11:36:13 -04:00
Fernando Sahmkow
dda6147b0d ARMInterface: Correct rebase errors. 2020-06-27 11:36:12 -04:00
Fernando Sahmkow
7b44187fd2 Dynarmic Interface: don't clear cache if JIT has not been created. 2020-06-27 11:36:08 -04:00
Fernando Sahmkow
48fa3b7a0f General: Cleanup legacy code. 2020-06-27 11:36:05 -04:00
Fernando Sahmkow
f5e32935ca SingleCore: Use Cycle Timing instead of Host Timing. 2020-06-27 11:36:01 -04:00
Fernando Sahmkow
1567824d2d General: Move ARM_Interface into Threads. 2020-06-27 11:35:58 -04:00
Fernando Sahmkow
1b82ccec22 Core: Refactor ARM Interface. 2020-06-27 11:35:56 -04:00
Fernando Sahmkow
534466754f X64 Clock: Reduce accuracy to be less or equal to guest accuracy. 2020-06-27 11:35:55 -04:00
Fernando Sahmkow
87c49aa7be SVC/ARM: Correct svcSendSyncRequest and cache ticks on arm interface. 2020-06-27 11:35:53 -04:00
Fernando Sahmkow
25565dffd5 ARM: Addapt to new Exclusive Monitor Interface. 2020-06-27 11:35:50 -04:00
Fernando Sahmkow
7020d498c5 General: Fix microprofile on dynarmic/svc, fix wait tree showing which threads were running. 2020-06-27 11:35:48 -04:00
Fernando Sahmkow
cd1c38be8d ARM/Memory: Correct Exclusive Monitor and Implement Exclusive Memory Writes. 2020-06-27 11:35:37 -04:00
Fernando Sahmkow
a33fbaddec Core: Correct rebase. 2020-06-27 11:35:29 -04:00
Fernando Sahmkow
e31425df38 General: Recover Prometheus project from harddrive failure
This commit: Implements CPU Interrupts, Replaces Cycle Timing for Host 
Timing, Reworks the Kernel's Scheduler, Introduce Idle State and 
Suspended State, Recreates the bootmanager, Initializes Multicore 
system.
2020-06-27 11:35:06 -04:00
Morph
f2df941e8d arm_dynarmic_64: Log the instruction when an exception is raised 2020-06-22 07:00:24 -04:00
Morph
e0af4cdf98 arm_dynarmic_32: Log under Core_ARM instead of HW_GPU 2020-06-22 06:59:41 -04:00
ReinUsesLisp
778043a44c arm_dynarmic_32: Fix implicit conversion error in SetTPIDR_EL0
On MSVC builds we treat conversion warnings as errors.
2020-06-18 16:52:15 -03:00
MerryMage
52bcfac116 arm_dynarmic_cp15: Implement CNTPCT 2020-06-17 17:10:24 +01:00
MerryMage
109df7705f arm_dynarmic_cp15: Update CP15 2020-06-17 17:10:24 +01:00
MerryMage
32a127faaa arm_dynarmic_32: InterpreterFallback should never happen 2020-06-17 17:10:24 +01:00
Lioncash
cc84b48ce5 physical_core: Make use of std::make_unique instead of std::make_shared in ctor
We can also allow unicorn to be constructed in 32-bit mode or 64-bit
mode to satisfy the need for both interpreter instances.

Allows this code to compile successfully of non x86-64 architectures.
2020-04-24 00:20:58 -04:00
MerryMage
a3a12deecc dynarmic: Add option to disable CPU JIT optimizations 2020-04-20 13:36:26 +01:00
bunnei
f1b607829e dynarmic: Enable strict alignment checks.
- Also add a missing include.
2020-04-17 00:59:29 -04:00
bunnei
4caff51710 core: memory: Move to Core::Memory namespace.
- helpful to disambiguate Kernel::Memory namespace.
2020-04-17 00:59:28 -04:00
bunnei
82d457af37 core: kernel: Move SVC to its own namesapce. 2020-04-17 00:59:28 -04:00
bunnei
c083ea7d78 core: Implement separate A32/A64 ARM interfaces. 2020-03-02 21:51:57 -05:00
bunnei
64facb403e core: dynarmic: Add CP15 from Citra. 2020-03-02 21:43:15 -05:00
Fernando Sahmkow
f3d4d4eaa8 ARM_Interface: Cache the JITs instead of deleting/recreating.
This was a bug inherited from citra which was fixed by then at some 
time. This commit corrects such bug and ensures JITs are correctly 
recycled.
2020-02-26 15:53:47 -04:00
Fernando Sahmkow
1e6f8aba04 Core: Set all hardware emulation constants in a single file. 2020-02-11 20:19:11 -04:00
Lioncash
472319e573 core/arm: Remove usage of global GetCurrentThread()
Now both CPU backends go through their referenced system instance to
obtain the current thread.
2020-01-30 18:52:25 -05:00
Fernando Sahmkow
e4a1ead897 Core: Refactor CpuCoreManager to CpuManager and Cpu to Core Manager.
This commit instends on better naming the new purpose of this classes.
2020-01-26 14:07:22 -04:00
Markus Wick
0986caa8d8 core/memory + arm/dynarmic: Use a global offset within our arm page table.
This saves us two x64 instructions per load/store instruction.

TODO: Clean up our memory code. We can use this optimization here as well.
2020-01-01 12:24:54 +01:00
Lioncash
e4c381b885 core/memory: Migrate over Write{8, 16, 32, 64, Block} to the Memory class
The Write functions are used slightly less than the Read functions,
which make these a bit nicer to move over.

The only adjustments we really need to make here are to Dynarmic's
exclusive monitor instance. We need to keep a reference to the currently
active memory instance to perform exclusive read/write operations.
2019-11-26 21:55:39 -05:00
Lioncash
b05bfc6036 core/memory: Migrate over Read{8, 16, 32, 64, Block} to the Memory class
With all of the trivial parts of the memory interface moved over, we can
get right into moving over the bits that are used.

Note that this does require the use of GetInstance from the global
system instance to be used within hle_ipc.cpp and the gdbstub. This is
fine for the time being, as they both already rely on the global system
instance in other functions. These will be removed in a change directed
at both of these respectively.

For now, it's sufficient, as it still accomplishes the goal of
de-globalizing the memory code.
2019-11-26 21:55:39 -05:00
Lioncash
536fc7f0ea core: Prepare various classes for memory read/write migration
Amends a few interfaces to be able to handle the migration over to the
new Memory class by passing the class by reference as a function
parameter where necessary.

Notably, within the filesystem services, this eliminates two ReadBlock()
calls by using the helper functions of HLERequestContext to do that for
us.
2019-11-26 21:55:37 -05:00
Lioncash
19a0abc19b arm_unicorn: Resolve sign conversion warnings
While we're at it, this also resolves a type truncation warning as well,
given the code was truncating from a 64-bit value to a 32-bit one.
2019-11-12 07:06:48 -05:00
Fernando Sahmkow
e0650a2034 Core_Timing: Address Feedback and suppress warnings. 2019-10-11 14:44:14 -04:00
Fernando Sahmkow
555866f8dc Core Timing: Rework Core Timing to run all cores evenly. 2019-10-09 12:30:31 -04:00
bunnei
dc29919bbe
Revert "arm_dynarmic: Check if jit is nullptr when preparing reschedule" 2019-09-29 21:54:19 -04:00
bunnei
28538bba9c
Merge pull request #2574 from DarkLordZach/dynarmic-jit-nullptr
arm_dynarmic: Check if jit is nullptr when preparing reschedule
2019-09-29 21:44:10 -04:00
Lioncash
70624e1c1d core/arm: Remove obsolete Unicorn memory mapping
This was initially necessary when AArch64 JIT emulation was in its
infancy and all memory-related instructions weren't implemented.

Given the JIT now has all of these facilities implemented, we can remove
these functions from the CPU interface.
2019-07-11 05:35:46 -04:00
Zach Hilman
425cdf946c arm_dynarmic: Check if jit is nullptr when preparing reschedule
Prevents crash with multiprocess loading.
2019-06-10 00:14:25 -04:00
Lioncash
f2331a804a core/cpu_core_manager: Create threads separately from initialization.
Our initialization process is a little wonky than one would expect when
it comes to code flow. We initialize the CPU last, as opposed to
hardware, where the CPU obviously needs to be first, otherwise nothing
else would work, and we have code that adds checks to get around this.

For example, in the page table setting code, we check to see if the
system is turned on before we even notify the CPU instances of a page
table switch. This results in dead code (at the moment), because the
only time a page table switch will occur is when the system is *not*
running, preventing the emulated CPU instances from being notified of a
page table switch in a convenient manner (technically the code path
could be taken, but we don't emulate the process creation svc handlers
yet).

This moves the threads creation into its own member function of the core
manager and restores a little order (and predictability) to our
initialization process.

Previously, in the multi-threaded cases, we'd kick off several threads
before even the main kernel process was created and ready to execute (gross!).
Now the initialization process is like so:

Initialization:
  1. Timers

  2. CPU

  3. Kernel

  4. Filesystem stuff (kind of gross, but can be amended trivially)

  5. Applet stuff (ditto in terms of being kind of gross)

  6. Main process (will be moved into the loading step in a following
                   change)

  7. Telemetry (this should be initialized last in the future).

  8. Services (4 and 5 should ideally be alongside this).

  9. GDB (gross. Uses namespace scope state. Needs to be refactored into a
          class or booted altogether).

  10. Renderer

  11. GPU (will also have its threads created in a separate step in a
           following change).

Which... isn't *ideal* per-se, however getting rid of the wonky
intertwining of CPU state initialization out of this mix gets rid of
most of the footguns when it comes to our initialization process.
2019-04-11 22:11:40 -04:00
Lioncash
b117ca5fce kernel/svc: Deglobalize the supervisor call handlers
Adjusts the interface of the wrappers to take a system reference, which
allows accessing a system instance without using the global accessors.

This also allows getting rid of all global accessors within the
supervisor call handling code. While this does make the wrappers
themselves slightly more noisy, this will be further cleaned up in a
follow-up. This eliminates the global system accessors in the current
code while preserving the existing interface.
2019-04-07 20:30:05 -04:00
Lioncash
a6a82bb004 arm/arm_dynarmic: Remove unnecessary current_page_table member
Given the page table will always be guaranteed to be that of whatever
the current process is, we no longer need to keep this around.
2019-04-07 02:43:51 -04:00
Lioncash
5b0a9f8ba8 core: Add missing override specifiers where applicable
Applies the override specifier where applicable. In the case of
destructors that are  defaulted in their definition, they can
simply be removed.

This also removes the unnecessary inclusions being done in audin_u and
audrec_u, given their close proximity.
2019-04-04 12:19:44 -04:00
bunnei
93da8e0abf core: Move PageTable struct into Common. 2019-03-16 22:05:40 -04:00
Fernando Sahmkow
a8d4927e29 Corrections, documenting and fixes. 2019-02-16 16:52:24 -04:00
Fernando Sahmkow
ecccfe0337 Use u128 on Clock Cycles calculation. 2019-02-15 22:57:16 -04:00
Fernando Sahmkow
5b7ec71fb7 Correct CNTPCT to use Clock Cycles instead of Cpu Cycles. 2019-02-15 22:55:29 -04:00
Lioncash
bd983414f6 core_timing: Convert core timing into a class
Gets rid of the largest set of mutable global state within the core.
This also paves a way for eliminating usages of GetInstance() on the
System class as a follow-up.

Note that no behavioral changes have been made, and this simply extracts
the functionality into a class. This also has the benefit of making
dependencies on the core timing functionality explicit within the
relevant interfaces.
2019-02-15 21:50:25 -05:00
Lioncash
48d9d66dc5 core_timing: Rename CoreTiming namespace to Core::Timing
Places all of the timing-related functionality under the existing Core
namespace to keep things consistent, rather than having the timing
utilities sitting in its own completely separate namespace.
2019-02-12 12:42:17 -05:00
MerryMage
fd2c42bfcd arm_dynarmic: Set CNTFRQ value 2018-12-18 17:28:12 +00:00