102 lines
4.2 KiB
C++
102 lines
4.2 KiB
C++
// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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using Tegra::Shader::ShuffleOperation;
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using Tegra::Shader::VoteOperation;
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namespace {
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OperationCode GetOperationCode(VoteOperation vote_op) {
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switch (vote_op) {
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case VoteOperation::All:
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return OperationCode::VoteAll;
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case VoteOperation::Any:
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return OperationCode::VoteAny;
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case VoteOperation::Eq:
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return OperationCode::VoteEqual;
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default:
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UNREACHABLE_MSG("Invalid vote operation={}", static_cast<u64>(vote_op));
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return OperationCode::VoteAll;
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}
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}
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} // Anonymous namespace
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u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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switch (opcode->get().GetId()) {
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case OpCode::Id::VOTE: {
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const Node value = GetPredicate(instr.vote.value, instr.vote.negate_value != 0);
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const Node active = Operation(OperationCode::BallotThread, value);
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const Node vote = Operation(GetOperationCode(instr.vote.operation), value);
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SetRegister(bb, instr.gpr0, active);
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SetPredicate(bb, instr.vote.dest_pred, vote);
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break;
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}
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case OpCode::Id::SHFL: {
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Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm))
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: GetRegister(instr.gpr39);
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Node width = [&] {
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// Convert the obscure SHFL mask back into GL_NV_shader_thread_shuffle's width. This has
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// been done reversing Nvidia's math. It won't work on all cases due to SHFL having
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// different parameters that don't properly map to GLSL's interface, but it should work
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// for cases emitted by Nvidia's compiler.
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if (instr.shfl.operation == ShuffleOperation::Up) {
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return Operation(
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OperationCode::ILogicalShiftRight,
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Operation(OperationCode::IAdd, std::move(mask), Immediate(-0x2000)),
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Immediate(8));
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} else {
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return Operation(OperationCode::ILogicalShiftRight,
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Operation(OperationCode::IAdd, Immediate(0x201F),
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Operation(OperationCode::INegate, std::move(mask))),
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Immediate(8));
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}
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}();
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const auto [operation, in_range] = [instr]() -> std::pair<OperationCode, OperationCode> {
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switch (instr.shfl.operation) {
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case ShuffleOperation::Idx:
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return {OperationCode::ShuffleIndexed, OperationCode::InRangeShuffleIndexed};
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case ShuffleOperation::Up:
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return {OperationCode::ShuffleUp, OperationCode::InRangeShuffleUp};
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case ShuffleOperation::Down:
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return {OperationCode::ShuffleDown, OperationCode::InRangeShuffleDown};
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case ShuffleOperation::Bfly:
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return {OperationCode::ShuffleButterfly, OperationCode::InRangeShuffleButterfly};
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}
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UNREACHABLE_MSG("Invalid SHFL operation: {}",
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static_cast<u64>(instr.shfl.operation.Value()));
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return {};
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}();
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// Setting the predicate before the register is intentional to avoid overwriting.
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Node index = instr.shfl.is_index_imm ? Immediate(static_cast<u32>(instr.shfl.index_imm))
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: GetRegister(instr.gpr20);
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SetPredicate(bb, instr.shfl.pred48, Operation(in_range, index, width));
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SetRegister(
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bb, instr.gpr0,
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Operation(operation, GetRegister(instr.gpr8), std::move(index), std::move(width)));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled warp instruction: {}", opcode->get().GetName());
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break;
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}
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return pc;
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}
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} // namespace VideoCommon::Shader
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