99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
351 lines
10 KiB
C++
351 lines
10 KiB
C++
// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <array>
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#include <cstddef>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/engines/engine_interface.h"
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#include "video_core/gpu.h"
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namespace Tegra {
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class MemoryManager;
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}
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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/**
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* This Engine is known as G80_2D. Documentation can be found in:
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* https://github.com/envytools/envytools/blob/master/rnndb/graph/g80_2d.xml
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* https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nv50/nv50_2d.xml.h
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*/
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#define FERMI2D_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::Fermi2D::Regs, field_name) / sizeof(u32))
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class Fermi2D final : public EngineInterface {
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public:
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explicit Fermi2D();
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~Fermi2D() override;
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/// Binds a rasterizer to this engine.
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void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
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/// Write the value to the register identified by method.
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void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
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/// Write multiple values to the register identified by method.
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void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
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u32 methods_pending) override;
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enum class Origin : u32 {
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Center = 0,
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Corner = 1,
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};
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enum class Filter : u32 {
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Point = 0,
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Bilinear = 1,
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};
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enum class Operation : u32 {
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SrcCopyAnd = 0,
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ROPAnd = 1,
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Blend = 2,
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SrcCopy = 3,
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ROP = 4,
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SrcCopyPremult = 5,
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BlendPremult = 6,
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};
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enum class MemoryLayout : u32 {
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BlockLinear = 0,
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Pitch = 1,
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};
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enum class CpuIndexWrap : u32 {
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Wrap = 0,
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NoWrap = 1,
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};
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struct Surface {
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RenderTargetFormat format;
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MemoryLayout linear;
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union {
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_depth;
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};
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u32 depth;
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u32 layer;
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u32 pitch;
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u32 width;
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u32 height;
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u32 addr_upper;
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u32 addr_lower;
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[[nodiscard]] constexpr GPUVAddr Address() const noexcept {
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return (static_cast<GPUVAddr>(addr_upper) << 32) | static_cast<GPUVAddr>(addr_lower);
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}
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};
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static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
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enum class SectorPromotion : u32 {
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NoPromotion = 0,
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PromoteTo2V = 1,
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PromoteTo2H = 2,
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PromoteTo4 = 3,
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};
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enum class NumTpcs : u32 {
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All = 0,
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One = 1,
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};
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enum class RenderEnableMode : u32 {
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False = 0,
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True = 1,
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Conditional = 2,
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RenderIfEqual = 3,
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RenderIfNotEqual = 4,
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};
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enum class ColorKeyFormat : u32 {
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A16R56G6B5 = 0,
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A1R5G55B5 = 1,
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A8R8G8B8 = 2,
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A2R10G10B10 = 3,
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Y8 = 4,
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Y16 = 5,
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Y32 = 6,
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};
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union Beta4 {
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BitField<0, 8, u32> b;
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BitField<8, 8, u32> g;
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BitField<16, 8, u32> r;
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BitField<24, 8, u32> a;
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};
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struct Point {
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u32 x;
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u32 y;
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};
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enum class PatternSelect : u32 {
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MonoChrome8x8 = 0,
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MonoChrome64x1 = 1,
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MonoChrome1x64 = 2,
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Color = 3,
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};
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enum class NotifyType : u32 {
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WriteOnly = 0,
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WriteThenAwaken = 1,
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};
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enum class MonochromePatternColorFormat : u32 {
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A8X8R8G6B5 = 0,
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A1R5G5B5 = 1,
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A8R8G8B8 = 2,
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A8Y8 = 3,
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A8X8Y16 = 4,
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Y32 = 5,
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};
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enum class MonochromePatternFormat : u32 {
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CGA6_M1 = 0,
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LE_M1 = 1,
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};
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union Regs {
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static constexpr std::size_t NUM_REGS = 0x258;
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struct {
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u32 object;
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INSERT_PADDING_WORDS_NOINIT(0x3F);
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u32 no_operation;
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NotifyType notify;
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INSERT_PADDING_WORDS_NOINIT(0x2);
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u32 wait_for_idle;
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INSERT_PADDING_WORDS_NOINIT(0xB);
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u32 pm_trigger;
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INSERT_PADDING_WORDS_NOINIT(0xF);
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u32 context_dma_notify;
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u32 dst_context_dma;
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u32 src_context_dma;
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u32 semaphore_context_dma;
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INSERT_PADDING_WORDS_NOINIT(0x1C);
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Surface dst;
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CpuIndexWrap pixels_from_cpu_index_wrap;
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u32 kind2d_check_enable;
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Surface src;
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SectorPromotion pixels_from_memory_sector_promotion;
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INSERT_PADDING_WORDS_NOINIT(0x1);
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NumTpcs num_tpcs;
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u32 render_enable_addr_upper;
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u32 render_enable_addr_lower;
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RenderEnableMode render_enable_mode;
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INSERT_PADDING_WORDS_NOINIT(0x4);
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u32 clip_x0;
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u32 clip_y0;
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u32 clip_width;
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u32 clip_height;
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BitField<0, 1, u32> clip_enable;
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BitField<0, 3, ColorKeyFormat> color_key_format;
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u32 color_key;
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BitField<0, 1, u32> color_key_enable;
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BitField<0, 8, u32> rop;
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u32 beta1;
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Beta4 beta4;
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Operation operation;
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union {
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BitField<0, 6, u32> x;
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BitField<8, 6, u32> y;
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} pattern_offset;
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BitField<0, 2, PatternSelect> pattern_select;
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INSERT_PADDING_WORDS_NOINIT(0xC);
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struct {
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BitField<0, 3, MonochromePatternColorFormat> color_format;
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BitField<0, 1, MonochromePatternFormat> format;
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u32 color0;
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u32 color1;
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u32 pattern0;
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u32 pattern1;
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} monochrome_pattern;
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struct {
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std::array<u32, 0x40> X8R8G8B8;
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std::array<u32, 0x20> R5G6B5;
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std::array<u32, 0x20> X1R5G5B5;
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std::array<u32, 0x10> Y8;
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} color_pattern;
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INSERT_PADDING_WORDS_NOINIT(0x10);
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struct {
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u32 prim_mode;
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u32 prim_color_format;
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u32 prim_color;
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u32 line_tie_break_bits;
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INSERT_PADDING_WORDS_NOINIT(0x14);
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u32 prim_point_xy;
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INSERT_PADDING_WORDS_NOINIT(0x7);
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std::array<Point, 0x40> prim_point;
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} render_solid;
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struct {
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u32 data_type;
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u32 color_format;
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u32 index_format;
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u32 mono_format;
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u32 wrap;
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u32 color0;
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u32 color1;
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u32 mono_opacity;
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INSERT_PADDING_WORDS_NOINIT(0x6);
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u32 src_width;
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u32 src_height;
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u32 dx_du_frac;
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u32 dx_du_int;
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u32 dx_dv_frac;
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u32 dy_dv_int;
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u32 dst_x0_frac;
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u32 dst_x0_int;
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u32 dst_y0_frac;
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u32 dst_y0_int;
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u32 data;
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} pixels_from_cpu;
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INSERT_PADDING_WORDS_NOINIT(0x3);
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u32 big_endian_control;
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INSERT_PADDING_WORDS_NOINIT(0x3);
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struct {
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BitField<0, 3, u32> block_shape;
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BitField<0, 5, u32> corral_size;
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BitField<0, 1, u32> safe_overlap;
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union {
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BitField<0, 1, Origin> origin;
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BitField<4, 1, Filter> filter;
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} sample_mode;
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INSERT_PADDING_WORDS_NOINIT(0x8);
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s32 dst_x0;
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s32 dst_y0;
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s32 dst_width;
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s32 dst_height;
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s64 du_dx;
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s64 dv_dy;
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s64 src_x0;
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s64 src_y0;
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} pixels_from_memory;
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};
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std::array<u32, NUM_REGS> reg_array;
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} regs{};
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struct Config {
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Operation operation;
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Filter filter;
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s32 dst_x0;
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s32 dst_y0;
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s32 dst_x1;
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s32 dst_y1;
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s32 src_x0;
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s32 src_y0;
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s32 src_x1;
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s32 src_y1;
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};
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private:
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VideoCore::RasterizerInterface* rasterizer = nullptr;
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/// Performs the copy from the source surface to the destination surface as configured in the
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/// registers.
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void Blit();
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Fermi2D::Regs, field_name) == position, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(object, 0x0);
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ASSERT_REG_POSITION(no_operation, 0x100);
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ASSERT_REG_POSITION(notify, 0x104);
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ASSERT_REG_POSITION(wait_for_idle, 0x110);
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ASSERT_REG_POSITION(pm_trigger, 0x140);
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ASSERT_REG_POSITION(context_dma_notify, 0x180);
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ASSERT_REG_POSITION(dst_context_dma, 0x184);
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ASSERT_REG_POSITION(src_context_dma, 0x188);
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ASSERT_REG_POSITION(semaphore_context_dma, 0x18C);
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ASSERT_REG_POSITION(dst, 0x200);
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ASSERT_REG_POSITION(pixels_from_cpu_index_wrap, 0x228);
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ASSERT_REG_POSITION(kind2d_check_enable, 0x22C);
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ASSERT_REG_POSITION(src, 0x230);
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ASSERT_REG_POSITION(pixels_from_memory_sector_promotion, 0x258);
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ASSERT_REG_POSITION(num_tpcs, 0x260);
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ASSERT_REG_POSITION(render_enable_addr_upper, 0x264);
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ASSERT_REG_POSITION(render_enable_addr_lower, 0x268);
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ASSERT_REG_POSITION(clip_x0, 0x280);
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ASSERT_REG_POSITION(clip_y0, 0x284);
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ASSERT_REG_POSITION(clip_width, 0x288);
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ASSERT_REG_POSITION(clip_height, 0x28c);
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ASSERT_REG_POSITION(clip_enable, 0x290);
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ASSERT_REG_POSITION(color_key_format, 0x294);
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ASSERT_REG_POSITION(color_key, 0x298);
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ASSERT_REG_POSITION(rop, 0x2A0);
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ASSERT_REG_POSITION(beta1, 0x2A4);
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ASSERT_REG_POSITION(beta4, 0x2A8);
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ASSERT_REG_POSITION(operation, 0x2AC);
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ASSERT_REG_POSITION(pattern_offset, 0x2B0);
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ASSERT_REG_POSITION(pattern_select, 0x2B4);
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ASSERT_REG_POSITION(monochrome_pattern, 0x2E8);
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ASSERT_REG_POSITION(color_pattern, 0x300);
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ASSERT_REG_POSITION(render_solid, 0x580);
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ASSERT_REG_POSITION(pixels_from_cpu, 0x800);
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ASSERT_REG_POSITION(big_endian_control, 0x870);
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ASSERT_REG_POSITION(pixels_from_memory, 0x880);
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#undef ASSERT_REG_POSITION
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} // namespace Tegra::Engines
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