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https://git.suyu.dev/suyu/suyu.git
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f9ee0dc7ee
Removes a few unnecessary dependencies on core-related machinery, such as the core.h and memory.h, which reduces the amount of rebuilding necessary if those files change. This also uncovered some indirect dependencies within other source files. This also fixes those.
147 lines
4.1 KiB
C++
147 lines
4.1 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <cstddef>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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#define FERMI2D_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::Fermi2D::Regs, field_name) / sizeof(u32))
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class Fermi2D final {
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public:
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explicit Fermi2D(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager);
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~Fermi2D() = default;
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/// Write the value to the register identified by method.
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void CallMethod(const GPU::MethodCall& method_call);
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struct Regs {
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static constexpr std::size_t NUM_REGS = 0x258;
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struct Surface {
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RenderTargetFormat format;
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BitField<0, 1, u32> linear;
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union {
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_depth;
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};
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u32 depth;
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u32 layer;
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u32 pitch;
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u32 width;
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u32 height;
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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u32 BlockWidth() const {
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// The block width is stored in log2 format.
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return 1 << block_width;
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}
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u32 BlockHeight() const {
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// The block height is stored in log2 format.
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return 1 << block_height;
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}
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u32 BlockDepth() const {
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// The block depth is stored in log2 format.
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return 1 << block_depth;
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}
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};
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static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
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enum class Operation : u32 {
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SrcCopyAnd = 0,
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ROPAnd = 1,
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Blend = 2,
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SrcCopy = 3,
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ROP = 4,
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SrcCopyPremult = 5,
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BlendPremult = 6,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0x80);
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Surface dst;
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INSERT_PADDING_WORDS(2);
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Surface src;
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INSERT_PADDING_WORDS(0x15);
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Operation operation;
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INSERT_PADDING_WORDS(0x177);
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u32 blit_control;
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INSERT_PADDING_WORDS(0x8);
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u32 blit_dst_x;
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u32 blit_dst_y;
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u32 blit_dst_width;
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u32 blit_dst_height;
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u64 blit_du_dx;
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u64 blit_dv_dy;
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u64 blit_src_x;
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u64 blit_src_y;
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INSERT_PADDING_WORDS(0x21);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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MemoryManager& memory_manager;
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private:
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VideoCore::RasterizerInterface& rasterizer;
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/// Performs the copy from the source surface to the destination surface as configured in the
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/// registers.
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void HandleSurfaceCopy();
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Fermi2D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(dst, 0x80);
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ASSERT_REG_POSITION(src, 0x8C);
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ASSERT_REG_POSITION(operation, 0xAB);
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ASSERT_REG_POSITION(blit_control, 0x223);
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ASSERT_REG_POSITION(blit_dst_x, 0x22c);
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ASSERT_REG_POSITION(blit_dst_y, 0x22d);
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ASSERT_REG_POSITION(blit_dst_width, 0x22e);
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ASSERT_REG_POSITION(blit_dst_height, 0x22f);
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ASSERT_REG_POSITION(blit_du_dx, 0x230);
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ASSERT_REG_POSITION(blit_dv_dy, 0x232);
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ASSERT_REG_POSITION(blit_src_x, 0x234);
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ASSERT_REG_POSITION(blit_src_y, 0x236);
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#undef ASSERT_REG_POSITION
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} // namespace Tegra::Engines
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