mirror of
https://git.suyu.dev/suyu/suyu.git
synced 2024-11-04 22:12:46 +01:00
8e56a84566
Previously, we were mixing the raw CPU frequency and CNTFRQ. The raw CPU frequency (1020 MHz) should've never been used as CNTPCT (whose frequency is CNTFRQ) is the only counter available.
573 lines
17 KiB
C++
573 lines
17 KiB
C++
// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <array>
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#include <atomic>
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#include <chrono>
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#include <condition_variable>
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#include <list>
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#include <memory>
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#include "common/assert.h"
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#include "common/microprofile.h"
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#include "common/settings.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/frontend/emu_window.h"
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#include "core/frontend/graphics_context.h"
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#include "core/hle/service/nvdrv/nvdata.h"
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#include "core/perf_stats.h"
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#include "video_core/cdma_pusher.h"
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#include "video_core/control/channel_state.h"
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#include "video_core/control/scheduler.h"
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#include "video_core/dma_pusher.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/kepler_memory.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/gpu.h"
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#include "video_core/gpu_thread.h"
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#include "video_core/host1x/host1x.h"
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#include "video_core/host1x/syncpoint_manager.h"
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#include "video_core/memory_manager.h"
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#include "video_core/renderer_base.h"
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#include "video_core/shader_notify.h"
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namespace Tegra {
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struct GPU::Impl {
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explicit Impl(GPU& gpu_, Core::System& system_, bool is_async_, bool use_nvdec_)
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: gpu{gpu_}, system{system_}, host1x{system.Host1x()}, use_nvdec{use_nvdec_},
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shader_notify{std::make_unique<VideoCore::ShaderNotify>()}, is_async{is_async_},
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gpu_thread{system_, is_async_}, scheduler{std::make_unique<Control::Scheduler>(gpu)} {}
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~Impl() = default;
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std::shared_ptr<Control::ChannelState> CreateChannel(s32 channel_id) {
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auto channel_state = std::make_shared<Tegra::Control::ChannelState>(channel_id);
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channels.emplace(channel_id, channel_state);
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scheduler->DeclareChannel(channel_state);
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return channel_state;
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}
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void BindChannel(s32 channel_id) {
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if (bound_channel == channel_id) {
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return;
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}
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auto it = channels.find(channel_id);
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ASSERT(it != channels.end());
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bound_channel = channel_id;
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current_channel = it->second.get();
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rasterizer->BindChannel(*current_channel);
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}
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std::shared_ptr<Control::ChannelState> AllocateChannel() {
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return CreateChannel(new_channel_id++);
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}
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void InitChannel(Control::ChannelState& to_init) {
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to_init.Init(system, gpu);
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to_init.BindRasterizer(rasterizer);
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rasterizer->InitializeChannel(to_init);
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}
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void InitAddressSpace(Tegra::MemoryManager& memory_manager) {
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memory_manager.BindRasterizer(rasterizer);
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}
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void ReleaseChannel(Control::ChannelState& to_release) {
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UNIMPLEMENTED();
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}
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/// Binds a renderer to the GPU.
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void BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer_) {
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renderer = std::move(renderer_);
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rasterizer = renderer->ReadRasterizer();
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host1x.MemoryManager().BindRasterizer(rasterizer);
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}
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/// Flush all current written commands into the host GPU for execution.
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void FlushCommands() {
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rasterizer->FlushCommands();
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}
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/// Synchronizes CPU writes with Host GPU memory.
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void InvalidateGPUCache() {
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rasterizer->InvalidateGPUCache();
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}
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/// Signal the ending of command list.
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void OnCommandListEnd() {
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rasterizer->ReleaseFences();
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}
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/// Request a host GPU memory flush from the CPU.
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template <typename Func>
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[[nodiscard]] u64 RequestSyncOperation(Func&& action) {
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std::unique_lock lck{sync_request_mutex};
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const u64 fence = ++last_sync_fence;
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sync_requests.emplace_back(action);
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return fence;
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}
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/// Obtains current flush request fence id.
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[[nodiscard]] u64 CurrentSyncRequestFence() const {
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return current_sync_fence.load(std::memory_order_relaxed);
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}
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void WaitForSyncOperation(const u64 fence) {
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std::unique_lock lck{sync_request_mutex};
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sync_request_cv.wait(lck, [this, fence] { return CurrentSyncRequestFence() >= fence; });
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}
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/// Tick pending requests within the GPU.
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void TickWork() {
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std::unique_lock lck{sync_request_mutex};
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while (!sync_requests.empty()) {
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auto request = std::move(sync_requests.front());
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sync_requests.pop_front();
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sync_request_mutex.unlock();
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request();
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current_sync_fence.fetch_add(1, std::memory_order_release);
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sync_request_mutex.lock();
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sync_request_cv.notify_all();
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}
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}
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/// Returns a reference to the Maxwell3D GPU engine.
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[[nodiscard]] Engines::Maxwell3D& Maxwell3D() {
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ASSERT(current_channel);
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return *current_channel->maxwell_3d;
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}
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/// Returns a const reference to the Maxwell3D GPU engine.
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[[nodiscard]] const Engines::Maxwell3D& Maxwell3D() const {
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ASSERT(current_channel);
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return *current_channel->maxwell_3d;
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}
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] Engines::KeplerCompute& KeplerCompute() {
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ASSERT(current_channel);
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return *current_channel->kepler_compute;
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}
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] const Engines::KeplerCompute& KeplerCompute() const {
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ASSERT(current_channel);
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return *current_channel->kepler_compute;
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}
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/// Returns a reference to the GPU DMA pusher.
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[[nodiscard]] Tegra::DmaPusher& DmaPusher() {
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ASSERT(current_channel);
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return *current_channel->dma_pusher;
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}
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/// Returns a const reference to the GPU DMA pusher.
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[[nodiscard]] const Tegra::DmaPusher& DmaPusher() const {
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ASSERT(current_channel);
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return *current_channel->dma_pusher;
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}
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/// Returns a reference to the underlying renderer.
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[[nodiscard]] VideoCore::RendererBase& Renderer() {
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return *renderer;
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}
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/// Returns a const reference to the underlying renderer.
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[[nodiscard]] const VideoCore::RendererBase& Renderer() const {
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return *renderer;
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}
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/// Returns a reference to the shader notifier.
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[[nodiscard]] VideoCore::ShaderNotify& ShaderNotify() {
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return *shader_notify;
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}
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/// Returns a const reference to the shader notifier.
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[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const {
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return *shader_notify;
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}
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[[nodiscard]] u64 GetTicks() const {
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// This values were reversed engineered by fincs from NVN
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// The GPU clock is 614.4 MHz
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using NsToGPUTickRatio = std::ratio<614'400'000, std::nano::den>;
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static_assert(NsToGPUTickRatio::num == 384 && NsToGPUTickRatio::den == 625);
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u64 nanoseconds = system.CoreTiming().GetGlobalTimeNs().count();
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if (Settings::values.use_fast_gpu_time.GetValue()) {
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nanoseconds /= 256;
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}
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return nanoseconds * NsToGPUTickRatio::num / NsToGPUTickRatio::den;
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}
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[[nodiscard]] bool IsAsync() const {
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return is_async;
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}
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[[nodiscard]] bool UseNvdec() const {
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return use_nvdec;
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}
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void RendererFrameEndNotify() {
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system.GetPerfStats().EndGameFrame();
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}
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/// Performs any additional setup necessary in order to begin GPU emulation.
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/// This can be used to launch any necessary threads and register any necessary
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/// core timing events.
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void Start() {
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gpu_thread.StartThread(*renderer, renderer->Context(), *scheduler);
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}
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void NotifyShutdown() {
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std::unique_lock lk{sync_mutex};
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shutting_down.store(true, std::memory_order::relaxed);
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sync_cv.notify_all();
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}
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/// Obtain the CPU Context
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void ObtainContext() {
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if (!cpu_context) {
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cpu_context = renderer->GetRenderWindow().CreateSharedContext();
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}
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cpu_context->MakeCurrent();
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}
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/// Release the CPU Context
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void ReleaseContext() {
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cpu_context->DoneCurrent();
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}
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/// Push GPU command entries to be processed
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void PushGPUEntries(s32 channel, Tegra::CommandList&& entries) {
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gpu_thread.SubmitList(channel, std::move(entries));
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}
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/// Push GPU command buffer entries to be processed
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void PushCommandBuffer(u32 id, Tegra::ChCommandHeaderList& entries) {
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if (!use_nvdec) {
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return;
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}
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if (!cdma_pushers.contains(id)) {
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cdma_pushers.insert_or_assign(id, std::make_unique<Tegra::CDmaPusher>(host1x));
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}
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// SubmitCommandBuffer would make the nvdec operations async, this is not currently working
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// TODO(ameerj): RE proper async nvdec operation
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// gpu_thread.SubmitCommandBuffer(std::move(entries));
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cdma_pushers[id]->ProcessEntries(std::move(entries));
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}
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/// Frees the CDMAPusher instance to free up resources
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void ClearCdmaInstance(u32 id) {
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const auto iter = cdma_pushers.find(id);
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if (iter != cdma_pushers.end()) {
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cdma_pushers.erase(iter);
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}
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}
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/// Swap buffers (render frame)
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void SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
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gpu_thread.SwapBuffers(framebuffer);
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}
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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void FlushRegion(VAddr addr, u64 size) {
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gpu_thread.FlushRegion(addr, size);
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}
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VideoCore::RasterizerDownloadArea OnCPURead(VAddr addr, u64 size) {
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auto raster_area = rasterizer->GetFlushArea(addr, size);
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if (raster_area.preemtive) {
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return raster_area;
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}
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raster_area.preemtive = true;
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const u64 fence = RequestSyncOperation([this, &raster_area]() {
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rasterizer->FlushRegion(raster_area.start_address,
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raster_area.end_address - raster_area.start_address);
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});
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gpu_thread.TickGPU();
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WaitForSyncOperation(fence);
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return raster_area;
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}
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/// Notify rasterizer that any caches of the specified region should be invalidated
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void InvalidateRegion(VAddr addr, u64 size) {
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gpu_thread.InvalidateRegion(addr, size);
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}
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/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
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void FlushAndInvalidateRegion(VAddr addr, u64 size) {
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gpu_thread.FlushAndInvalidateRegion(addr, size);
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}
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void RequestSwapBuffers(const Tegra::FramebufferConfig* framebuffer,
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std::array<Service::Nvidia::NvFence, 4>& fences, size_t num_fences) {
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size_t current_request_counter{};
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{
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std::unique_lock<std::mutex> lk(request_swap_mutex);
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if (free_swap_counters.empty()) {
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current_request_counter = request_swap_counters.size();
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request_swap_counters.emplace_back(num_fences);
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} else {
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current_request_counter = free_swap_counters.front();
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request_swap_counters[current_request_counter] = num_fences;
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free_swap_counters.pop_front();
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}
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}
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const auto wait_fence =
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RequestSyncOperation([this, current_request_counter, framebuffer, fences, num_fences] {
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auto& syncpoint_manager = host1x.GetSyncpointManager();
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if (num_fences == 0) {
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renderer->SwapBuffers(framebuffer);
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}
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const auto executer = [this, current_request_counter,
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framebuffer_copy = *framebuffer]() {
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{
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std::unique_lock<std::mutex> lk(request_swap_mutex);
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if (--request_swap_counters[current_request_counter] != 0) {
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return;
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}
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free_swap_counters.push_back(current_request_counter);
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}
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renderer->SwapBuffers(&framebuffer_copy);
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};
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for (size_t i = 0; i < num_fences; i++) {
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syncpoint_manager.RegisterGuestAction(fences[i].id, fences[i].value, executer);
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}
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});
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gpu_thread.TickGPU();
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WaitForSyncOperation(wait_fence);
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}
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GPU& gpu;
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Core::System& system;
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Host1x::Host1x& host1x;
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std::map<u32, std::unique_ptr<Tegra::CDmaPusher>> cdma_pushers;
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std::unique_ptr<VideoCore::RendererBase> renderer;
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VideoCore::RasterizerInterface* rasterizer = nullptr;
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const bool use_nvdec;
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s32 new_channel_id{1};
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/// Shader build notifier
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std::unique_ptr<VideoCore::ShaderNotify> shader_notify;
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/// When true, we are about to shut down emulation session, so terminate outstanding tasks
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std::atomic_bool shutting_down{};
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std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
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std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
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std::mutex sync_mutex;
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std::mutex device_mutex;
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std::condition_variable sync_cv;
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std::list<std::function<void()>> sync_requests;
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std::atomic<u64> current_sync_fence{};
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u64 last_sync_fence{};
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std::mutex sync_request_mutex;
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std::condition_variable sync_request_cv;
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const bool is_async;
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VideoCommon::GPUThread::ThreadManager gpu_thread;
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std::unique_ptr<Core::Frontend::GraphicsContext> cpu_context;
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std::unique_ptr<Tegra::Control::Scheduler> scheduler;
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std::unordered_map<s32, std::shared_ptr<Tegra::Control::ChannelState>> channels;
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Tegra::Control::ChannelState* current_channel;
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s32 bound_channel{-1};
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std::deque<size_t> free_swap_counters;
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std::deque<size_t> request_swap_counters;
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std::mutex request_swap_mutex;
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};
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GPU::GPU(Core::System& system, bool is_async, bool use_nvdec)
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: impl{std::make_unique<Impl>(*this, system, is_async, use_nvdec)} {}
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GPU::~GPU() = default;
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std::shared_ptr<Control::ChannelState> GPU::AllocateChannel() {
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return impl->AllocateChannel();
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}
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void GPU::InitChannel(Control::ChannelState& to_init) {
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impl->InitChannel(to_init);
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}
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void GPU::BindChannel(s32 channel_id) {
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impl->BindChannel(channel_id);
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}
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void GPU::ReleaseChannel(Control::ChannelState& to_release) {
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impl->ReleaseChannel(to_release);
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}
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void GPU::InitAddressSpace(Tegra::MemoryManager& memory_manager) {
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impl->InitAddressSpace(memory_manager);
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}
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void GPU::BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer) {
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impl->BindRenderer(std::move(renderer));
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}
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void GPU::FlushCommands() {
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impl->FlushCommands();
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}
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void GPU::InvalidateGPUCache() {
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impl->InvalidateGPUCache();
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}
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void GPU::OnCommandListEnd() {
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impl->OnCommandListEnd();
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}
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u64 GPU::RequestFlush(VAddr addr, std::size_t size) {
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return impl->RequestSyncOperation(
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[this, addr, size]() { impl->rasterizer->FlushRegion(addr, size); });
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}
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u64 GPU::CurrentSyncRequestFence() const {
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return impl->CurrentSyncRequestFence();
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}
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void GPU::WaitForSyncOperation(u64 fence) {
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return impl->WaitForSyncOperation(fence);
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}
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void GPU::TickWork() {
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impl->TickWork();
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}
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/// Gets a mutable reference to the Host1x interface
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Host1x::Host1x& GPU::Host1x() {
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return impl->host1x;
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}
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/// Gets an immutable reference to the Host1x interface.
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const Host1x::Host1x& GPU::Host1x() const {
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return impl->host1x;
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}
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Engines::Maxwell3D& GPU::Maxwell3D() {
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return impl->Maxwell3D();
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}
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const Engines::Maxwell3D& GPU::Maxwell3D() const {
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return impl->Maxwell3D();
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}
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Engines::KeplerCompute& GPU::KeplerCompute() {
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return impl->KeplerCompute();
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}
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const Engines::KeplerCompute& GPU::KeplerCompute() const {
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return impl->KeplerCompute();
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}
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Tegra::DmaPusher& GPU::DmaPusher() {
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return impl->DmaPusher();
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}
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const Tegra::DmaPusher& GPU::DmaPusher() const {
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return impl->DmaPusher();
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}
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VideoCore::RendererBase& GPU::Renderer() {
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return impl->Renderer();
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}
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const VideoCore::RendererBase& GPU::Renderer() const {
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return impl->Renderer();
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}
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VideoCore::ShaderNotify& GPU::ShaderNotify() {
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return impl->ShaderNotify();
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}
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const VideoCore::ShaderNotify& GPU::ShaderNotify() const {
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return impl->ShaderNotify();
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}
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void GPU::RequestSwapBuffers(const Tegra::FramebufferConfig* framebuffer,
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std::array<Service::Nvidia::NvFence, 4>& fences, size_t num_fences) {
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impl->RequestSwapBuffers(framebuffer, fences, num_fences);
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}
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u64 GPU::GetTicks() const {
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return impl->GetTicks();
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}
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bool GPU::IsAsync() const {
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return impl->IsAsync();
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}
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bool GPU::UseNvdec() const {
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return impl->UseNvdec();
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}
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void GPU::RendererFrameEndNotify() {
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impl->RendererFrameEndNotify();
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}
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void GPU::Start() {
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impl->Start();
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}
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|
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void GPU::NotifyShutdown() {
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|
impl->NotifyShutdown();
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|
}
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|
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void GPU::ObtainContext() {
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|
impl->ObtainContext();
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|
}
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|
|
|
void GPU::ReleaseContext() {
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|
impl->ReleaseContext();
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|
}
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|
|
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void GPU::PushGPUEntries(s32 channel, Tegra::CommandList&& entries) {
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|
impl->PushGPUEntries(channel, std::move(entries));
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|
}
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|
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void GPU::PushCommandBuffer(u32 id, Tegra::ChCommandHeaderList& entries) {
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|
impl->PushCommandBuffer(id, entries);
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|
}
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|
|
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void GPU::ClearCdmaInstance(u32 id) {
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|
impl->ClearCdmaInstance(id);
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|
}
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|
|
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void GPU::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
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|
impl->SwapBuffers(framebuffer);
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|
}
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|
|
|
VideoCore::RasterizerDownloadArea GPU::OnCPURead(VAddr addr, u64 size) {
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|
return impl->OnCPURead(addr, size);
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|
}
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|
|
|
void GPU::FlushRegion(VAddr addr, u64 size) {
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|
impl->FlushRegion(addr, size);
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|
}
|
|
|
|
void GPU::InvalidateRegion(VAddr addr, u64 size) {
|
|
impl->InvalidateRegion(addr, size);
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|
}
|
|
|
|
void GPU::FlushAndInvalidateRegion(VAddr addr, u64 size) {
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|
impl->FlushAndInvalidateRegion(addr, size);
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|
}
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|
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} // namespace Tegra
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