818ba32746
Added license header back in. I originally removed this because I mostly rewrote the file, but meh
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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armmmu.c - Memory Management Unit emulation.
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ARMulator extensions for the ARM7100 family.
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Copyright (C) 1999 Ben Williamson
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ARMMMU_H_
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#define _ARMMMU_H_
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#define WORD_SHT 2
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#define WORD_SIZE (1<<WORD_SHT)
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/* The MMU is accessible with MCR and MRC operations to copro 15: */
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#define MMU_COPRO (15)
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/* Register numbers in the MMU: */
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typedef enum mmu_regnum_t
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{
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MMU_ID = 0,
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MMU_CONTROL = 1,
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MMU_TRANSLATION_TABLE_BASE = 2,
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MMU_DOMAIN_ACCESS_CONTROL = 3,
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MMU_FAULT_STATUS = 5,
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MMU_FAULT_ADDRESS = 6,
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MMU_CACHE_OPS = 7,
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MMU_TLB_OPS = 8,
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MMU_CACHE_LOCKDOWN = 9,
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MMU_TLB_LOCKDOWN = 10,
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MMU_PID = 13,
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/*MMU_V4 */
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MMU_V4_CACHE_OPS = 7,
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MMU_V4_TLB_OPS = 8,
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/*MMU_V3 */
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MMU_V3_FLUSH_TLB = 5,
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MMU_V3_FLUSH_TLB_ENTRY = 6,
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MMU_V3_FLUSH_CACHE = 7,
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/*MMU Intel SA-1100 */
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MMU_SA_RB_OPS = 9,
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MMU_SA_DEBUG = 14,
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MMU_SA_CP15_R15 = 15,
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//chy 2003-08-24
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/*Intel xscale CP15 */
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XSCALE_CP15_CACHE_TYPE = 0,
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XSCALE_CP15_AUX_CONTROL = 1,
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XSCALE_CP15_COPRO_ACCESS = 15,
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} mmu_regnum_t;
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/* Bits in the control register */
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#define CONTROL_MMU (1<<0)
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#define CONTROL_ALIGN_FAULT (1<<1)
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#define CONTROL_CACHE (1<<2)
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#define CONTROL_DATA_CACHE (1<<2)
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#define CONTROL_WRITE_BUFFER (1<<3)
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#define CONTROL_BIG_ENDIAN (1<<7)
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#define CONTROL_SYSTEM (1<<8)
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#define CONTROL_ROM (1<<9)
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#define CONTROL_UNDEFINED (1<<10)
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#define CONTROL_BRANCH_PREDICT (1<<11)
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#define CONTROL_INSTRUCTION_CACHE (1<<12)
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#define CONTROL_VECTOR (1<<13)
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#define CONTROL_RR (1<<14)
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#define CONTROL_L4 (1<<15)
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#define CONTROL_XP (1<<23)
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#define CONTROL_EE (1<<25)
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/*Macro defines for MMU state*/
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#define MMU_CTL (state->mmu.control)
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#define MMU_Enabled (state->mmu.control & CONTROL_MMU)
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#define MMU_Disabled (!(MMU_Enabled))
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#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT)
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#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE)
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#define MMU_ICacheDisabled (!(MMU_ICacheDisabled))
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#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE)
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#define MMU_DCacheDisabled (!(MMU_DCacheEnabled))
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#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE)
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#define MMU_CacheDisabled (!(MMU_CacheEnabled))
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#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER)
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#define MMU_WBDisabled (!(MMU_WBEnabled))
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/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
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#define PID_VA_MAP_MASK 0xfe000000
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//#define mmu_pid_va_map(va) ({\
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// ARMword ret; \
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// if ((va) & PID_VA_MAP_MASK)\
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// ret = (va); \
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// else \
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// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
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// ret;\
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//})
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#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))
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/* FS[3:0] in the fault status register: */
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typedef enum fault_t
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{
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NO_FAULT = 0x0,
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ALIGNMENT_FAULT = 0x1,
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SECTION_TRANSLATION_FAULT = 0x5,
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PAGE_TRANSLATION_FAULT = 0x7,
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SECTION_DOMAIN_FAULT = 0x9,
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PAGE_DOMAIN_FAULT = 0xB,
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SECTION_PERMISSION_FAULT = 0xD,
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SUBPAGE_PERMISSION_FAULT = 0xF,
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/* defined by skyeye */
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TLB_READ_MISS = 0x30,
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TLB_WRITE_MISS = 0x40,
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} fault_t;
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#endif /* _ARMMMU_H_ */
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