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82 lines
3.6 KiB
C++
82 lines
3.6 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/memory.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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Fermi2D::Fermi2D(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
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: memory_manager(memory_manager), rasterizer{rasterizer} {}
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void Fermi2D::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Fermi2D register, increase the size of the Regs structure");
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regs.reg_array[method] = value;
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switch (method) {
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case FERMI2D_REG_INDEX(trigger): {
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HandleSurfaceCopy();
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break;
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}
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}
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}
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void Fermi2D::HandleSurfaceCopy() {
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LOG_WARNING(HW_GPU, "Requested a surface copy with operation {}",
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static_cast<u32>(regs.operation));
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const GPUVAddr source = regs.src.Address();
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const GPUVAddr dest = regs.dst.Address();
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// TODO(Subv): Only same-format and same-size copies are allowed for now.
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ASSERT(regs.src.format == regs.dst.format);
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ASSERT(regs.src.width * regs.src.height == regs.dst.width * regs.dst.height);
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// TODO(Subv): Only raw copies are implemented.
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ASSERT(regs.operation == Regs::Operation::SrcCopy);
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const VAddr source_cpu = *memory_manager.GpuToCpuAddress(source);
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const VAddr dest_cpu = *memory_manager.GpuToCpuAddress(dest);
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u32 src_bytes_per_pixel = RenderTargetBytesPerPixel(regs.src.format);
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u32 dst_bytes_per_pixel = RenderTargetBytesPerPixel(regs.dst.format);
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if (!rasterizer.AccelerateSurfaceCopy(regs.src, regs.dst)) {
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rasterizer.FlushRegion(source_cpu, src_bytes_per_pixel * regs.src.width * regs.src.height);
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// We have to invalidate the destination region to evict any outdated surfaces from the
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// cache. We do this before actually writing the new data because the destination address
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// might contain a dirty surface that will have to be written back to memory.
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rasterizer.InvalidateRegion(dest_cpu,
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dst_bytes_per_pixel * regs.dst.width * regs.dst.height);
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if (regs.src.linear == regs.dst.linear) {
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// If the input layout and the output layout are the same, just perform a raw copy.
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ASSERT(regs.src.BlockHeight() == regs.dst.BlockHeight());
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Memory::CopyBlock(dest_cpu, source_cpu,
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src_bytes_per_pixel * regs.dst.width * regs.dst.height);
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return;
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}
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u8* src_buffer = Memory::GetPointer(source_cpu);
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u8* dst_buffer = Memory::GetPointer(dest_cpu);
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if (!regs.src.linear && regs.dst.linear) {
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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Texture::CopySwizzledData(regs.src.width, regs.src.height, regs.src.depth,
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src_bytes_per_pixel, dst_bytes_per_pixel, src_buffer,
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dst_buffer, true, regs.src.BlockHeight(),
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regs.src.BlockDepth(), 0);
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} else {
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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Texture::CopySwizzledData(regs.src.width, regs.src.height, regs.src.depth,
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src_bytes_per_pixel, dst_bytes_per_pixel, dst_buffer,
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src_buffer, false, regs.dst.BlockHeight(),
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regs.dst.BlockDepth(), 0);
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}
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}
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}
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} // namespace Tegra::Engines
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