117 lines
4.5 KiB
C++
117 lines
4.5 KiB
C++
// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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using Tegra::Shader::ShuffleOperation;
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using Tegra::Shader::VoteOperation;
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namespace {
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OperationCode GetOperationCode(VoteOperation vote_op) {
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switch (vote_op) {
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case VoteOperation::All:
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return OperationCode::VoteAll;
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case VoteOperation::Any:
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return OperationCode::VoteAny;
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case VoteOperation::Eq:
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return OperationCode::VoteEqual;
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default:
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UNREACHABLE_MSG("Invalid vote operation={}", static_cast<u64>(vote_op));
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return OperationCode::VoteAll;
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}
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}
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} // Anonymous namespace
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u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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// Signal the backend that this shader uses warp instructions.
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uses_warps = true;
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switch (opcode->get().GetId()) {
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case OpCode::Id::VOTE: {
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const Node value = GetPredicate(instr.vote.value, instr.vote.negate_value != 0);
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const Node active = Operation(OperationCode::BallotThread, value);
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const Node vote = Operation(GetOperationCode(instr.vote.operation), value);
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SetRegister(bb, instr.gpr0, active);
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SetPredicate(bb, instr.vote.dest_pred, vote);
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break;
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}
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case OpCode::Id::SHFL: {
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Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm))
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: GetRegister(instr.gpr39);
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Node index = instr.shfl.is_index_imm ? Immediate(static_cast<u32>(instr.shfl.index_imm))
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: GetRegister(instr.gpr20);
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Node thread_id = Operation(OperationCode::ThreadId);
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Node clamp = Operation(OperationCode::IBitwiseAnd, mask, Immediate(0x1FU));
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Node seg_mask = BitfieldExtract(mask, 8, 16);
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Node neg_seg_mask = Operation(OperationCode::IBitwiseNot, seg_mask);
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Node min_thread_id = Operation(OperationCode::IBitwiseAnd, thread_id, seg_mask);
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Node max_thread_id = Operation(OperationCode::IBitwiseOr, min_thread_id,
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Operation(OperationCode::IBitwiseAnd, clamp, neg_seg_mask));
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Node src_thread_id = [instr, index, neg_seg_mask, min_thread_id, thread_id] {
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switch (instr.shfl.operation) {
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case ShuffleOperation::Idx:
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return Operation(OperationCode::IBitwiseOr,
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Operation(OperationCode::IBitwiseAnd, index, neg_seg_mask),
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min_thread_id);
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case ShuffleOperation::Down:
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return Operation(OperationCode::IAdd, thread_id, index);
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case ShuffleOperation::Up:
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return Operation(OperationCode::IAdd, thread_id,
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Operation(OperationCode::INegate, index));
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case ShuffleOperation::Bfly:
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return Operation(OperationCode::IBitwiseXor, thread_id, index);
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}
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UNREACHABLE();
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return Immediate(0U);
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}();
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Node in_bounds = [instr, src_thread_id, min_thread_id, max_thread_id] {
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if (instr.shfl.operation == ShuffleOperation::Up) {
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return Operation(OperationCode::LogicalIGreaterEqual, src_thread_id, min_thread_id);
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} else {
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return Operation(OperationCode::LogicalILessEqual, src_thread_id, max_thread_id);
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}
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}();
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SetPredicate(bb, instr.shfl.pred48, in_bounds);
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SetRegister(
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bb, instr.gpr0,
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Operation(OperationCode::ShuffleIndexed, GetRegister(instr.gpr8), src_thread_id));
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break;
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}
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case OpCode::Id::FSWZADD: {
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UNIMPLEMENTED_IF(instr.fswzadd.ndv);
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Node op_a = GetRegister(instr.gpr8);
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Node op_b = GetRegister(instr.gpr20);
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Node mask = Immediate(static_cast<u32>(instr.fswzadd.swizzle));
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SetRegister(bb, instr.gpr0, Operation(OperationCode::FSwizzleAdd, op_a, op_b, mask));
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled warp instruction: {}", opcode->get().GetName());
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break;
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}
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return pc;
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}
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} // namespace VideoCommon::Shader
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