2018-01-13 22:22:39 +01:00
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// Copyright 2018 yuzu emulator team
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2016-09-02 05:07:14 +02:00
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2018-01-13 23:34:15 +01:00
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#include <cinttypes>
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2018-01-09 22:33:46 +01:00
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#include <memory>
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#include <dynarmic/A64/a64.h>
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#include <dynarmic/A64/config.h>
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2020-11-04 01:54:53 +01:00
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#include "common/assert.h"
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2018-02-21 21:48:22 +01:00
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#include "common/logging/log.h"
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2020-04-03 03:36:26 +02:00
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#include "common/page_table.h"
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2021-04-15 01:07:40 +02:00
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#include "common/settings.h"
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2020-02-25 03:04:12 +01:00
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#include "core/arm/cpu_interrupt_handler.h"
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2020-03-02 05:46:10 +01:00
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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2020-06-19 01:56:59 +02:00
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#include "core/arm/dynarmic/arm_exclusive_monitor.h"
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2018-03-13 22:49:59 +01:00
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#include "core/core.h"
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2018-01-09 22:33:46 +01:00
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#include "core/core_timing.h"
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2020-02-12 00:56:24 +01:00
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#include "core/hardware_properties.h"
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2021-04-24 07:04:28 +02:00
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#include "core/hle/kernel/k_process.h"
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2020-12-03 03:08:35 +01:00
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#include "core/hle/kernel/k_scheduler.h"
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2018-01-09 22:33:46 +01:00
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#include "core/hle/kernel/svc.h"
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#include "core/memory.h"
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2018-08-25 03:43:32 +02:00
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namespace Core {
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2018-02-09 01:04:05 +01:00
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using Vector = Dynarmic::A64::Vector;
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2020-03-02 05:46:10 +01:00
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class DynarmicCallbacks64 : public Dynarmic::A64::UserCallbacks {
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public:
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explicit DynarmicCallbacks64(ARM_Dynarmic_64& parent_) : parent{parent_} {}
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2018-01-09 22:33:46 +01:00
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2018-01-13 23:34:15 +01:00
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u8 MemoryRead8(u64 vaddr) override {
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2019-11-26 22:29:34 +01:00
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return parent.system.Memory().Read8(vaddr);
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2018-01-09 22:33:46 +01:00
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}
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2018-01-13 23:34:15 +01:00
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u16 MemoryRead16(u64 vaddr) override {
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2019-11-26 22:29:34 +01:00
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return parent.system.Memory().Read16(vaddr);
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2018-01-09 22:33:46 +01:00
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}
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2018-01-13 23:34:15 +01:00
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u32 MemoryRead32(u64 vaddr) override {
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2019-11-26 22:29:34 +01:00
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return parent.system.Memory().Read32(vaddr);
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2018-01-09 22:33:46 +01:00
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}
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2018-01-13 23:34:15 +01:00
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u64 MemoryRead64(u64 vaddr) override {
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2019-11-26 22:29:34 +01:00
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return parent.system.Memory().Read64(vaddr);
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2018-01-09 22:33:46 +01:00
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}
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2018-02-09 01:04:05 +01:00
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Vector MemoryRead128(u64 vaddr) override {
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2019-11-26 22:29:34 +01:00
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auto& memory = parent.system.Memory();
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return {memory.Read64(vaddr), memory.Read64(vaddr + 8)};
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2018-02-09 01:04:05 +01:00
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}
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2018-01-09 22:33:46 +01:00
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2018-01-13 23:34:15 +01:00
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void MemoryWrite8(u64 vaddr, u8 value) override {
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2019-11-26 23:39:57 +01:00
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parent.system.Memory().Write8(vaddr, value);
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2018-01-09 22:33:46 +01:00
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}
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2018-01-13 23:34:15 +01:00
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void MemoryWrite16(u64 vaddr, u16 value) override {
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2019-11-26 23:39:57 +01:00
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parent.system.Memory().Write16(vaddr, value);
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2018-01-09 22:33:46 +01:00
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}
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2018-01-13 23:34:15 +01:00
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void MemoryWrite32(u64 vaddr, u32 value) override {
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2019-11-26 23:39:57 +01:00
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parent.system.Memory().Write32(vaddr, value);
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2018-01-09 22:33:46 +01:00
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}
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2018-01-13 23:34:15 +01:00
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void MemoryWrite64(u64 vaddr, u64 value) override {
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2019-11-26 23:39:57 +01:00
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parent.system.Memory().Write64(vaddr, value);
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2018-01-09 22:33:46 +01:00
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}
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2018-02-09 01:04:05 +01:00
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void MemoryWrite128(u64 vaddr, Vector value) override {
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2019-11-26 23:39:57 +01:00
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auto& memory = parent.system.Memory();
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memory.Write64(vaddr, value[0]);
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memory.Write64(vaddr + 8, value[1]);
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2018-02-09 01:04:05 +01:00
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}
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2018-01-09 22:33:46 +01:00
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2020-03-07 23:59:42 +01:00
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bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, std::uint8_t expected) override {
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return parent.system.Memory().WriteExclusive8(vaddr, value, expected);
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}
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bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, std::uint16_t expected) override {
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return parent.system.Memory().WriteExclusive16(vaddr, value, expected);
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}
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bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, std::uint32_t expected) override {
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return parent.system.Memory().WriteExclusive32(vaddr, value, expected);
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}
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bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, std::uint64_t expected) override {
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return parent.system.Memory().WriteExclusive64(vaddr, value, expected);
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}
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bool MemoryWriteExclusive128(u64 vaddr, Vector value, Vector expected) override {
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return parent.system.Memory().WriteExclusive128(vaddr, value, expected);
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}
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2018-09-15 15:21:06 +02:00
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void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
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2020-11-04 01:54:53 +01:00
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LOG_ERROR(Core_ARM,
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"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, MemoryReadCode(pc));
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2018-01-09 22:33:46 +01:00
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}
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2018-02-09 01:04:05 +01:00
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
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switch (exception) {
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case Dynarmic::A64::Exception::WaitForInterrupt:
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case Dynarmic::A64::Exception::WaitForEvent:
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case Dynarmic::A64::Exception::SendEvent:
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case Dynarmic::A64::Exception::SendEventLocal:
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case Dynarmic::A64::Exception::Yield:
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return;
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2018-09-19 21:40:31 +02:00
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case Dynarmic::A64::Exception::Breakpoint:
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
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default:
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2020-06-22 13:00:24 +02:00
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ASSERT_MSG(false, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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static_cast<std::size_t>(exception), pc, MemoryReadCode(pc));
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
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}
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2018-01-13 23:34:15 +01:00
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}
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void CallSVC(u32 swi) override {
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2021-05-27 22:54:22 +02:00
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parent.svc_called = true;
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parent.svc_swi = swi;
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parent.jit->HaltExecution();
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2018-01-09 22:33:46 +01:00
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}
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2018-01-13 23:34:15 +01:00
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void AddTicks(u64 ticks) override {
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2020-03-28 20:23:28 +01:00
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if (parent.uses_wall_clock) {
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return;
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}
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2020-11-04 01:54:53 +01:00
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2020-03-28 20:23:28 +01:00
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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// if not all cores are doing a similar amount of work. Instead of doing this, we should
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// device a way so that timing is consistent across all cores without increasing the ticks 4
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// times.
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2020-11-04 01:54:53 +01:00
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u64 amortized_ticks = ticks / Core::Hardware::NUM_CPU_CORES;
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2020-03-28 20:23:28 +01:00
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// Always execute at least one tick.
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amortized_ticks = std::max<u64>(amortized_ticks, 1);
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parent.system.CoreTiming().AddTicks(amortized_ticks);
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2018-01-09 22:33:46 +01:00
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}
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2020-03-20 17:36:01 +01:00
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2018-01-13 23:34:15 +01:00
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u64 GetTicksRemaining() override {
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2020-03-28 20:23:28 +01:00
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if (parent.uses_wall_clock) {
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if (!parent.interrupt_handlers[parent.core_index].IsInterrupted()) {
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2020-06-28 00:20:06 +02:00
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return minimum_run_cycles;
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2020-03-28 20:23:28 +01:00
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}
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2020-05-14 20:48:50 +02:00
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return 0U;
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2020-02-25 03:04:12 +01:00
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}
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2020-10-21 04:07:39 +02:00
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return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
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2018-01-09 22:33:46 +01:00
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}
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2020-03-20 17:36:01 +01:00
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
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u64 GetCNTPCT() override {
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2020-02-25 03:04:12 +01:00
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return parent.system.CoreTiming().GetClockTicks();
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
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}
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2018-01-09 22:33:46 +01:00
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2020-03-02 05:46:10 +01:00
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ARM_Dynarmic_64& parent;
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2018-02-12 22:53:32 +01:00
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u64 tpidrro_el0 = 0;
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dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
|
|
|
u64 tpidr_el0 = 0;
|
2020-06-28 00:20:06 +02:00
|
|
|
static constexpr u64 minimum_run_cycles = 1000U;
|
2018-01-09 22:33:46 +01:00
|
|
|
};
|
|
|
|
|
2021-03-24 12:08:41 +01:00
|
|
|
std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable* page_table,
|
2020-03-02 05:46:10 +01:00
|
|
|
std::size_t address_space_bits) const {
|
2018-02-12 22:53:32 +01:00
|
|
|
Dynarmic::A64::UserConfig config;
|
2018-07-03 15:28:46 +02:00
|
|
|
|
|
|
|
// Callbacks
|
2018-02-12 22:53:32 +01:00
|
|
|
config.callbacks = cb.get();
|
2018-07-03 15:28:46 +02:00
|
|
|
|
|
|
|
// Memory
|
2021-03-24 12:08:41 +01:00
|
|
|
if (page_table) {
|
|
|
|
config.page_table = reinterpret_cast<void**>(page_table->pointers.data());
|
|
|
|
config.page_table_address_space_bits = address_space_bits;
|
|
|
|
config.page_table_pointer_mask_bits = Common::PageTable::ATTRIBUTE_BITS;
|
|
|
|
config.silently_mirror_page_table = false;
|
|
|
|
config.absolute_offset_page_table = true;
|
|
|
|
config.detect_misaligned_access_via_page_table = 16 | 32 | 64 | 128;
|
|
|
|
config.only_detect_misalignment_via_page_table_on_page_boundary = true;
|
|
|
|
}
|
2018-07-03 15:28:46 +02:00
|
|
|
|
|
|
|
// Multi-process state
|
|
|
|
config.processor_id = core_index;
|
2018-10-15 14:53:01 +02:00
|
|
|
config.global_monitor = &exclusive_monitor.monitor;
|
2018-07-03 15:28:46 +02:00
|
|
|
|
|
|
|
// System registers
|
2018-02-12 22:53:32 +01:00
|
|
|
config.tpidrro_el0 = &cb->tpidrro_el0;
|
dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
|
|
|
config.tpidr_el0 = &cb->tpidr_el0;
|
2018-02-12 22:53:32 +01:00
|
|
|
config.dczid_el0 = 4;
|
dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
|
|
|
config.ctr_el0 = 0x8444c004;
|
2020-02-12 00:56:24 +01:00
|
|
|
config.cntfrq_el0 = Hardware::CNTFREQ;
|
dynarmic: Update to 6b4c6b0
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:51:54 +01:00
|
|
|
|
2018-08-16 11:12:20 +02:00
|
|
|
// Unpredictable instructions
|
|
|
|
config.define_unpredictable_behaviour = true;
|
|
|
|
|
2020-05-03 04:03:09 +02:00
|
|
|
// Timing
|
2020-03-28 20:23:28 +01:00
|
|
|
config.wall_clock_cntpct = uses_wall_clock;
|
2020-03-21 17:23:13 +01:00
|
|
|
|
2021-04-02 19:08:39 +02:00
|
|
|
// Code cache size
|
|
|
|
config.code_cache_size = 512 * 1024 * 1024;
|
|
|
|
config.far_code_offset = 256 * 1024 * 1024;
|
|
|
|
|
2020-07-11 15:26:36 +02:00
|
|
|
// Safe optimizations
|
2021-05-16 02:46:48 +02:00
|
|
|
if (Settings::values.cpu_accuracy.GetValue() == Settings::CPUAccuracy::DebugMode) {
|
2020-07-11 17:25:49 +02:00
|
|
|
if (!Settings::values.cpuopt_page_tables) {
|
|
|
|
config.page_table = nullptr;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_block_linking) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::BlockLinking;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_return_stack_buffer) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::ReturnStackBuffer;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_fast_dispatcher) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::FastDispatch;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_context_elimination) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::GetSetElimination;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_const_prop) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::ConstProp;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_misc_ir) {
|
|
|
|
config.optimizations &= ~Dynarmic::OptimizationFlag::MiscIROpt;
|
|
|
|
}
|
|
|
|
if (!Settings::values.cpuopt_reduce_misalign_checks) {
|
|
|
|
config.only_detect_misalignment_via_page_table_on_page_boundary = false;
|
|
|
|
}
|
2020-07-11 15:26:36 +02:00
|
|
|
}
|
|
|
|
|
2020-08-16 14:19:55 +02:00
|
|
|
// Unsafe optimizations
|
2021-05-16 02:46:48 +02:00
|
|
|
if (Settings::values.cpu_accuracy.GetValue() == Settings::CPUAccuracy::Unsafe) {
|
2020-08-16 14:19:55 +02:00
|
|
|
config.unsafe_optimizations = true;
|
2021-05-16 02:46:48 +02:00
|
|
|
if (Settings::values.cpuopt_unsafe_unfuse_fma.GetValue()) {
|
2020-08-16 14:19:55 +02:00
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_UnfuseFMA;
|
|
|
|
}
|
2021-05-16 02:46:48 +02:00
|
|
|
if (Settings::values.cpuopt_unsafe_reduce_fp_error.GetValue()) {
|
2020-08-16 14:19:55 +02:00
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_ReducedErrorFP;
|
|
|
|
}
|
2021-05-16 02:46:48 +02:00
|
|
|
if (Settings::values.cpuopt_unsafe_inaccurate_nan.GetValue()) {
|
2021-01-02 18:36:02 +01:00
|
|
|
config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_InaccurateNaN;
|
|
|
|
}
|
2020-08-16 14:19:55 +02:00
|
|
|
}
|
|
|
|
|
2020-02-26 20:53:47 +01:00
|
|
|
return std::make_shared<Dynarmic::A64::Jit>(config);
|
2018-02-09 01:04:05 +01:00
|
|
|
}
|
|
|
|
|
2020-03-12 21:48:43 +01:00
|
|
|
void ARM_Dynarmic_64::Run() {
|
2021-05-27 22:54:22 +02:00
|
|
|
while (true) {
|
|
|
|
jit->Run();
|
|
|
|
if (!svc_called) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
svc_called = false;
|
|
|
|
Kernel::Svc::Call(system, svc_swi);
|
|
|
|
if (shutdown) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2020-11-13 20:11:12 +01:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::Step() {
|
2018-02-14 18:47:48 +01:00
|
|
|
cb->InterpreterFallback(jit->GetPC(), 1);
|
|
|
|
}
|
|
|
|
|
2021-05-04 10:04:05 +02:00
|
|
|
ARM_Dynarmic_64::ARM_Dynarmic_64(System& system_, CPUInterrupts& interrupt_handlers_,
|
|
|
|
bool uses_wall_clock_, ExclusiveMonitor& exclusive_monitor_,
|
|
|
|
std::size_t core_index_)
|
|
|
|
: ARM_Interface{system_, interrupt_handlers_, uses_wall_clock_},
|
|
|
|
cb(std::make_unique<DynarmicCallbacks64>(*this)), core_index{core_index_},
|
|
|
|
exclusive_monitor{dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor_)},
|
2021-03-24 12:08:41 +01:00
|
|
|
jit(MakeJit(nullptr, 48)) {}
|
2018-01-09 22:33:46 +01:00
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
ARM_Dynarmic_64::~ARM_Dynarmic_64() = default;
|
2018-01-09 22:33:46 +01:00
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::SetPC(u64 pc) {
|
2018-02-09 01:04:05 +01:00
|
|
|
jit->SetPC(pc);
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
u64 ARM_Dynarmic_64::GetPC() const {
|
2018-02-09 01:04:05 +01:00
|
|
|
return jit->GetPC();
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-10-21 04:07:39 +02:00
|
|
|
u64 ARM_Dynarmic_64::GetReg(int index) const {
|
2018-02-09 01:04:05 +01:00
|
|
|
return jit->GetRegister(index);
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-10-21 04:07:39 +02:00
|
|
|
void ARM_Dynarmic_64::SetReg(int index, u64 value) {
|
2018-02-09 01:04:05 +01:00
|
|
|
jit->SetRegister(index, value);
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-10-21 04:07:39 +02:00
|
|
|
u128 ARM_Dynarmic_64::GetVectorReg(int index) const {
|
2018-02-09 01:04:05 +01:00
|
|
|
return jit->GetVector(index);
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-10-21 04:07:39 +02:00
|
|
|
void ARM_Dynarmic_64::SetVectorReg(int index, u128 value) {
|
2018-02-09 01:04:05 +01:00
|
|
|
jit->SetVector(index, value);
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
u32 ARM_Dynarmic_64::GetPSTATE() const {
|
2018-02-09 01:04:05 +01:00
|
|
|
return jit->GetPstate();
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::SetPSTATE(u32 pstate) {
|
2018-09-18 08:49:40 +02:00
|
|
|
jit->SetPstate(pstate);
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
u64 ARM_Dynarmic_64::GetTlsAddress() const {
|
2018-02-12 22:53:32 +01:00
|
|
|
return cb->tpidrro_el0;
|
2017-09-30 20:16:39 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::SetTlsAddress(VAddr address) {
|
2018-02-12 22:53:32 +01:00
|
|
|
cb->tpidrro_el0 = address;
|
2017-09-30 20:16:39 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
u64 ARM_Dynarmic_64::GetTPIDR_EL0() const {
|
2018-07-21 02:57:45 +02:00
|
|
|
return cb->tpidr_el0;
|
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
|
2018-07-21 02:57:45 +02:00
|
|
|
cb->tpidr_el0 = value;
|
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
|
2018-02-09 01:04:05 +01:00
|
|
|
ctx.cpu_registers = jit->GetRegisters();
|
|
|
|
ctx.sp = jit->GetSP();
|
|
|
|
ctx.pc = jit->GetPC();
|
2018-09-18 08:49:40 +02:00
|
|
|
ctx.pstate = jit->GetPstate();
|
|
|
|
ctx.vector_registers = jit->GetVectors();
|
|
|
|
ctx.fpcr = jit->GetFpcr();
|
2018-09-29 23:58:26 +02:00
|
|
|
ctx.fpsr = jit->GetFpsr();
|
|
|
|
ctx.tpidr = cb->tpidr_el0;
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
|
2018-02-09 01:04:05 +01:00
|
|
|
jit->SetRegisters(ctx.cpu_registers);
|
|
|
|
jit->SetSP(ctx.sp);
|
|
|
|
jit->SetPC(ctx.pc);
|
2018-09-29 23:58:26 +02:00
|
|
|
jit->SetPstate(ctx.pstate);
|
2018-09-18 08:49:40 +02:00
|
|
|
jit->SetVectors(ctx.vector_registers);
|
2018-09-29 23:58:26 +02:00
|
|
|
jit->SetFpcr(ctx.fpcr);
|
|
|
|
jit->SetFpsr(ctx.fpsr);
|
|
|
|
SetTPIDR_EL0(ctx.tpidr);
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::PrepareReschedule() {
|
2018-08-13 14:59:01 +02:00
|
|
|
jit->HaltExecution();
|
2021-05-27 22:54:22 +02:00
|
|
|
shutdown = true;
|
2016-09-02 05:07:14 +02:00
|
|
|
}
|
|
|
|
|
2020-03-02 05:46:10 +01:00
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|
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void ARM_Dynarmic_64::ClearInstructionCache() {
|
2018-02-09 01:04:05 +01:00
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|
jit->ClearCache();
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2016-09-02 05:07:14 +02:00
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}
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2017-09-24 23:44:13 +02:00
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|
|
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2020-11-14 08:20:32 +01:00
|
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void ARM_Dynarmic_64::InvalidateCacheRange(VAddr addr, std::size_t size) {
|
|
|
|
jit->InvalidateCacheRange(addr, size);
|
|
|
|
}
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|
|
|
|
2020-03-02 05:46:10 +01:00
|
|
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void ARM_Dynarmic_64::ClearExclusiveState() {
|
2018-07-16 12:24:00 +02:00
|
|
|
jit->ClearExclusiveState();
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|
|
|
}
|
|
|
|
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2020-03-02 05:46:10 +01:00
|
|
|
void ARM_Dynarmic_64::PageTableChanged(Common::PageTable& page_table,
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|
|
|
std::size_t new_address_space_size_in_bits) {
|
2021-03-21 23:25:25 +01:00
|
|
|
ThreadContext64 ctx{};
|
|
|
|
SaveContext(ctx);
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|
|
|
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2020-02-26 20:53:47 +01:00
|
|
|
auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
|
|
|
|
auto iter = jit_cache.find(key);
|
|
|
|
if (iter != jit_cache.end()) {
|
|
|
|
jit = iter->second;
|
2021-03-21 23:25:25 +01:00
|
|
|
LoadContext(ctx);
|
2020-02-26 20:53:47 +01:00
|
|
|
return;
|
|
|
|
}
|
2021-03-24 12:08:41 +01:00
|
|
|
jit = MakeJit(&page_table, new_address_space_size_in_bits);
|
2021-03-21 23:25:25 +01:00
|
|
|
LoadContext(ctx);
|
2020-02-26 20:53:47 +01:00
|
|
|
jit_cache.emplace(key, jit);
|
2017-09-24 23:44:13 +02:00
|
|
|
}
|
2018-07-03 15:28:46 +02:00
|
|
|
|
2018-08-25 03:43:32 +02:00
|
|
|
} // namespace Core
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