1136 lines
45 KiB
C++
1136 lines
45 KiB
C++
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// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <array>
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#include <memory>
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#include <mutex>
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#include <vector>
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#include <boost/container/static_vector.hpp>
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#include <boost/functional/hash.hpp>
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "core/core.h"
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#include "core/memory.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/renderer_vulkan/declarations.h"
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#include "video_core/renderer_vulkan/fixed_pipeline_state.h"
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#include "video_core/renderer_vulkan/maxwell_to_vk.h"
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#include "video_core/renderer_vulkan/renderer_vulkan.h"
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#include "video_core/renderer_vulkan/vk_buffer_cache.h"
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#include "video_core/renderer_vulkan/vk_compute_pass.h"
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#include "video_core/renderer_vulkan/vk_compute_pipeline.h"
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#include "video_core/renderer_vulkan/vk_descriptor_pool.h"
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#include "video_core/renderer_vulkan/vk_device.h"
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#include "video_core/renderer_vulkan/vk_graphics_pipeline.h"
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#include "video_core/renderer_vulkan/vk_pipeline_cache.h"
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#include "video_core/renderer_vulkan/vk_rasterizer.h"
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#include "video_core/renderer_vulkan/vk_renderpass_cache.h"
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#include "video_core/renderer_vulkan/vk_resource_manager.h"
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#include "video_core/renderer_vulkan/vk_sampler_cache.h"
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#include "video_core/renderer_vulkan/vk_scheduler.h"
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#include "video_core/renderer_vulkan/vk_staging_buffer_pool.h"
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#include "video_core/renderer_vulkan/vk_texture_cache.h"
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#include "video_core/renderer_vulkan/vk_update_descriptor.h"
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namespace Vulkan {
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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MICROPROFILE_DEFINE(Vulkan_WaitForWorker, "Vulkan", "Wait for worker", MP_RGB(255, 192, 192));
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MICROPROFILE_DEFINE(Vulkan_Drawing, "Vulkan", "Record drawing", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_Compute, "Vulkan", "Record compute", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_Clearing, "Vulkan", "Record clearing", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_Geometry, "Vulkan", "Setup geometry", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_ConstBuffers, "Vulkan", "Setup constant buffers", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_GlobalBuffers, "Vulkan", "Setup global buffers", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_RenderTargets, "Vulkan", "Setup render targets", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_Textures, "Vulkan", "Setup textures", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_Images, "Vulkan", "Setup images", MP_RGB(192, 128, 128));
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MICROPROFILE_DEFINE(Vulkan_PipelineCache, "Vulkan", "Pipeline cache", MP_RGB(192, 128, 128));
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namespace {
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constexpr auto ComputeShaderIndex = static_cast<std::size_t>(Tegra::Engines::ShaderType::Compute);
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vk::Viewport GetViewportState(const VKDevice& device, const Maxwell& regs, std::size_t index) {
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const auto& viewport = regs.viewport_transform[index];
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const float x = viewport.translate_x - viewport.scale_x;
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const float y = viewport.translate_y - viewport.scale_y;
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const float width = viewport.scale_x * 2.0f;
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const float height = viewport.scale_y * 2.0f;
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const float reduce_z = regs.depth_mode == Maxwell::DepthMode::MinusOneToOne;
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float near = viewport.translate_z - viewport.scale_z * reduce_z;
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float far = viewport.translate_z + viewport.scale_z;
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if (!device.IsExtDepthRangeUnrestrictedSupported()) {
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near = std::clamp(near, 0.0f, 1.0f);
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far = std::clamp(far, 0.0f, 1.0f);
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}
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return vk::Viewport(x, y, width != 0 ? width : 1.0f, height != 0 ? height : 1.0f, near, far);
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}
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constexpr vk::Rect2D GetScissorState(const Maxwell& regs, std::size_t index) {
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const auto& scissor = regs.scissor_test[index];
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if (!scissor.enable) {
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return {{0, 0}, {INT32_MAX, INT32_MAX}};
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}
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const u32 width = scissor.max_x - scissor.min_x;
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const u32 height = scissor.max_y - scissor.min_y;
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return {{static_cast<s32>(scissor.min_x), static_cast<s32>(scissor.min_y)}, {width, height}};
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}
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std::array<GPUVAddr, Maxwell::MaxShaderProgram> GetShaderAddresses(
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const std::array<Shader, Maxwell::MaxShaderProgram>& shaders) {
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std::array<GPUVAddr, Maxwell::MaxShaderProgram> addresses;
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for (std::size_t i = 0; i < std::size(addresses); ++i) {
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addresses[i] = shaders[i] ? shaders[i]->GetGpuAddr() : 0;
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}
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return addresses;
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}
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void TransitionImages(const std::vector<ImageView>& views, vk::PipelineStageFlags pipeline_stage,
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vk::AccessFlags access) {
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for (auto& [view, layout] : views) {
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view->Transition(*layout, pipeline_stage, access);
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}
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}
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template <typename Engine, typename Entry>
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Tegra::Texture::FullTextureInfo GetTextureInfo(const Engine& engine, const Entry& entry,
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std::size_t stage) {
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const auto stage_type = static_cast<Tegra::Engines::ShaderType>(stage);
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if (entry.IsBindless()) {
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const Tegra::Texture::TextureHandle tex_handle =
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engine.AccessConstBuffer32(stage_type, entry.GetBuffer(), entry.GetOffset());
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return engine.GetTextureInfo(tex_handle);
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}
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if constexpr (std::is_same_v<Engine, Tegra::Engines::Maxwell3D>) {
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return engine.GetStageTexture(stage_type, entry.GetOffset());
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} else {
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return engine.GetTexture(entry.GetOffset());
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}
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}
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} // Anonymous namespace
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class BufferBindings final {
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public:
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void AddVertexBinding(const vk::Buffer* buffer, vk::DeviceSize offset) {
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vertex.buffer_ptrs[vertex.num_buffers] = buffer;
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vertex.offsets[vertex.num_buffers] = offset;
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++vertex.num_buffers;
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}
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void SetIndexBinding(const vk::Buffer* buffer, vk::DeviceSize offset, vk::IndexType type) {
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index.buffer = buffer;
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index.offset = offset;
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index.type = type;
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}
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void Bind(VKScheduler& scheduler) const {
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// Use this large switch case to avoid dispatching more memory in the record lambda than
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// what we need. It looks horrible, but it's the best we can do on standard C++.
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switch (vertex.num_buffers) {
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case 0:
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return BindStatic<0>(scheduler);
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case 1:
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return BindStatic<1>(scheduler);
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case 2:
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return BindStatic<2>(scheduler);
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case 3:
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return BindStatic<3>(scheduler);
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case 4:
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return BindStatic<4>(scheduler);
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case 5:
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return BindStatic<5>(scheduler);
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case 6:
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return BindStatic<6>(scheduler);
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case 7:
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return BindStatic<7>(scheduler);
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case 8:
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return BindStatic<8>(scheduler);
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case 9:
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return BindStatic<9>(scheduler);
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case 10:
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return BindStatic<10>(scheduler);
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case 11:
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return BindStatic<11>(scheduler);
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case 12:
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return BindStatic<12>(scheduler);
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case 13:
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return BindStatic<13>(scheduler);
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case 14:
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return BindStatic<14>(scheduler);
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case 15:
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return BindStatic<15>(scheduler);
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case 16:
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return BindStatic<16>(scheduler);
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case 17:
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return BindStatic<17>(scheduler);
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case 18:
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return BindStatic<18>(scheduler);
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case 19:
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return BindStatic<19>(scheduler);
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case 20:
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return BindStatic<20>(scheduler);
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case 21:
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return BindStatic<21>(scheduler);
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case 22:
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return BindStatic<22>(scheduler);
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case 23:
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return BindStatic<23>(scheduler);
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case 24:
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return BindStatic<24>(scheduler);
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case 25:
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return BindStatic<25>(scheduler);
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case 26:
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return BindStatic<26>(scheduler);
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case 27:
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return BindStatic<27>(scheduler);
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case 28:
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return BindStatic<28>(scheduler);
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case 29:
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return BindStatic<29>(scheduler);
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case 30:
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return BindStatic<30>(scheduler);
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case 31:
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return BindStatic<31>(scheduler);
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}
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UNREACHABLE();
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}
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private:
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// Some of these fields are intentionally left uninitialized to avoid initializing them twice.
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struct {
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std::size_t num_buffers = 0;
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std::array<const vk::Buffer*, Maxwell::NumVertexArrays> buffer_ptrs;
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std::array<vk::DeviceSize, Maxwell::NumVertexArrays> offsets;
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} vertex;
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struct {
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const vk::Buffer* buffer = nullptr;
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vk::DeviceSize offset;
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vk::IndexType type;
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} index;
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template <std::size_t N>
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void BindStatic(VKScheduler& scheduler) const {
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if (index.buffer != nullptr) {
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BindStatic<N, true>(scheduler);
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} else {
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BindStatic<N, false>(scheduler);
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}
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}
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template <std::size_t N, bool is_indexed>
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void BindStatic(VKScheduler& scheduler) const {
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static_assert(N <= Maxwell::NumVertexArrays);
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if constexpr (N == 0) {
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return;
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}
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std::array<vk::Buffer, N> buffers;
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std::transform(vertex.buffer_ptrs.begin(), vertex.buffer_ptrs.begin() + N, buffers.begin(),
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[](const auto ptr) { return *ptr; });
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std::array<vk::DeviceSize, N> offsets;
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std::copy(vertex.offsets.begin(), vertex.offsets.begin() + N, offsets.begin());
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if constexpr (is_indexed) {
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// Indexed draw
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scheduler.Record([buffers, offsets, index_buffer = *index.buffer,
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index_offset = index.offset,
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index_type = index.type](auto cmdbuf, auto& dld) {
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cmdbuf.bindIndexBuffer(index_buffer, index_offset, index_type, dld);
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cmdbuf.bindVertexBuffers(0, static_cast<u32>(N), buffers.data(), offsets.data(),
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dld);
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});
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} else {
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// Array draw
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scheduler.Record([buffers, offsets](auto cmdbuf, auto& dld) {
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cmdbuf.bindVertexBuffers(0, static_cast<u32>(N), buffers.data(), offsets.data(),
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dld);
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});
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}
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}
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};
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void RasterizerVulkan::DrawParameters::Draw(vk::CommandBuffer cmdbuf,
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const vk::DispatchLoaderDynamic& dld) const {
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if (is_indexed) {
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cmdbuf.drawIndexed(num_vertices, num_instances, 0, base_vertex, base_instance, dld);
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} else {
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cmdbuf.draw(num_vertices, num_instances, base_vertex, base_instance, dld);
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}
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}
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RasterizerVulkan::RasterizerVulkan(Core::System& system, Core::Frontend::EmuWindow& renderer,
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VKScreenInfo& screen_info, const VKDevice& device,
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VKResourceManager& resource_manager,
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VKMemoryManager& memory_manager, VKScheduler& scheduler)
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: RasterizerAccelerated{system.Memory()}, system{system}, render_window{renderer},
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screen_info{screen_info}, device{device}, resource_manager{resource_manager},
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memory_manager{memory_manager}, scheduler{scheduler},
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staging_pool(device, memory_manager, scheduler), descriptor_pool(device),
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update_descriptor_queue(device, scheduler),
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quad_array_pass(device, scheduler, descriptor_pool, staging_pool, update_descriptor_queue),
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uint8_pass(device, scheduler, descriptor_pool, staging_pool, update_descriptor_queue),
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texture_cache(system, *this, device, resource_manager, memory_manager, scheduler,
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staging_pool),
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pipeline_cache(system, *this, device, scheduler, descriptor_pool, update_descriptor_queue),
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buffer_cache(*this, system, device, memory_manager, scheduler, staging_pool),
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sampler_cache(device) {}
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RasterizerVulkan::~RasterizerVulkan() = default;
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bool RasterizerVulkan::DrawBatch(bool is_indexed) {
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Draw(is_indexed, false);
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return true;
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}
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bool RasterizerVulkan::DrawMultiBatch(bool is_indexed) {
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Draw(is_indexed, true);
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return true;
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}
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void RasterizerVulkan::Draw(bool is_indexed, bool is_instanced) {
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MICROPROFILE_SCOPE(Vulkan_Drawing);
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FlushWork();
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const auto& gpu = system.GPU().Maxwell3D();
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GraphicsPipelineCacheKey key{GetFixedPipelineState(gpu.regs)};
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buffer_cache.Map(CalculateGraphicsStreamBufferSize(is_indexed));
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BufferBindings buffer_bindings;
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const DrawParameters draw_params =
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SetupGeometry(key.fixed_state, buffer_bindings, is_indexed, is_instanced);
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update_descriptor_queue.Acquire();
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sampled_views.clear();
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image_views.clear();
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const auto shaders = pipeline_cache.GetShaders();
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key.shaders = GetShaderAddresses(shaders);
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SetupShaderDescriptors(shaders);
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buffer_cache.Unmap();
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const auto texceptions = UpdateAttachments();
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SetupImageTransitions(texceptions, color_attachments, zeta_attachment);
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key.renderpass_params = GetRenderPassParams(texceptions);
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auto& pipeline = pipeline_cache.GetGraphicsPipeline(key);
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scheduler.BindGraphicsPipeline(pipeline.GetHandle());
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const auto renderpass = pipeline.GetRenderPass();
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const auto [framebuffer, render_area] = ConfigureFramebuffers(renderpass);
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scheduler.RequestRenderpass({renderpass, framebuffer, {{0, 0}, render_area}, 0, nullptr});
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UpdateDynamicStates();
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buffer_bindings.Bind(scheduler);
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if (device.IsNvDeviceDiagnosticCheckpoints()) {
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scheduler.Record(
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[&pipeline](auto cmdbuf, auto& dld) { cmdbuf.setCheckpointNV(&pipeline, dld); });
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}
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const auto pipeline_layout = pipeline.GetLayout();
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const auto descriptor_set = pipeline.CommitDescriptorSet();
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scheduler.Record([pipeline_layout, descriptor_set, draw_params](auto cmdbuf, auto& dld) {
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if (descriptor_set) {
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cmdbuf.bindDescriptorSets(vk::PipelineBindPoint::eGraphics, pipeline_layout,
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DESCRIPTOR_SET, 1, &descriptor_set, 0, nullptr, dld);
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}
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draw_params.Draw(cmdbuf, dld);
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});
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}
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void RasterizerVulkan::Clear() {
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MICROPROFILE_SCOPE(Vulkan_Clearing);
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const auto& gpu = system.GPU().Maxwell3D();
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if (!system.GPU().Maxwell3D().ShouldExecute()) {
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return;
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}
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const auto& regs = gpu.regs;
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const bool use_color = regs.clear_buffers.R || regs.clear_buffers.G || regs.clear_buffers.B ||
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regs.clear_buffers.A;
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const bool use_depth = regs.clear_buffers.Z;
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const bool use_stencil = regs.clear_buffers.S;
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if (!use_color && !use_depth && !use_stencil) {
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return;
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}
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// Clearing images requires to be out of a renderpass
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scheduler.RequestOutsideRenderPassOperationContext();
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// TODO(Rodrigo): Implement clears rendering a quad or using beginning a renderpass.
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if (use_color) {
|
||
|
View color_view;
|
||
|
{
|
||
|
MICROPROFILE_SCOPE(Vulkan_RenderTargets);
|
||
|
color_view = texture_cache.GetColorBufferSurface(regs.clear_buffers.RT.Value(), false);
|
||
|
}
|
||
|
|
||
|
color_view->Transition(vk::ImageLayout::eTransferDstOptimal,
|
||
|
vk::PipelineStageFlagBits::eTransfer,
|
||
|
vk::AccessFlagBits::eTransferWrite);
|
||
|
|
||
|
const std::array clear_color = {regs.clear_color[0], regs.clear_color[1],
|
||
|
regs.clear_color[2], regs.clear_color[3]};
|
||
|
const vk::ClearColorValue clear(clear_color);
|
||
|
scheduler.Record([image = color_view->GetImage(),
|
||
|
subresource = color_view->GetImageSubresourceRange(),
|
||
|
clear](auto cmdbuf, auto& dld) {
|
||
|
cmdbuf.clearColorImage(image, vk::ImageLayout::eTransferDstOptimal, clear, subresource,
|
||
|
dld);
|
||
|
});
|
||
|
}
|
||
|
if (use_depth || use_stencil) {
|
||
|
View zeta_surface;
|
||
|
{
|
||
|
MICROPROFILE_SCOPE(Vulkan_RenderTargets);
|
||
|
zeta_surface = texture_cache.GetDepthBufferSurface(false);
|
||
|
}
|
||
|
|
||
|
zeta_surface->Transition(vk::ImageLayout::eTransferDstOptimal,
|
||
|
vk::PipelineStageFlagBits::eTransfer,
|
||
|
vk::AccessFlagBits::eTransferWrite);
|
||
|
|
||
|
const vk::ClearDepthStencilValue clear(regs.clear_depth,
|
||
|
static_cast<u32>(regs.clear_stencil));
|
||
|
scheduler.Record([image = zeta_surface->GetImage(),
|
||
|
subresource = zeta_surface->GetImageSubresourceRange(),
|
||
|
clear](auto cmdbuf, auto& dld) {
|
||
|
cmdbuf.clearDepthStencilImage(image, vk::ImageLayout::eTransferDstOptimal, clear,
|
||
|
subresource, dld);
|
||
|
});
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::DispatchCompute(GPUVAddr code_addr) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_Compute);
|
||
|
update_descriptor_queue.Acquire();
|
||
|
sampled_views.clear();
|
||
|
image_views.clear();
|
||
|
|
||
|
const auto& launch_desc = system.GPU().KeplerCompute().launch_description;
|
||
|
const ComputePipelineCacheKey key{
|
||
|
code_addr,
|
||
|
launch_desc.shared_alloc,
|
||
|
{launch_desc.block_dim_x, launch_desc.block_dim_y, launch_desc.block_dim_z}};
|
||
|
auto& pipeline = pipeline_cache.GetComputePipeline(key);
|
||
|
|
||
|
// Compute dispatches can't be executed inside a renderpass
|
||
|
scheduler.RequestOutsideRenderPassOperationContext();
|
||
|
|
||
|
buffer_cache.Map(CalculateComputeStreamBufferSize());
|
||
|
|
||
|
const auto& entries = pipeline.GetEntries();
|
||
|
SetupComputeConstBuffers(entries);
|
||
|
SetupComputeGlobalBuffers(entries);
|
||
|
SetupComputeTexelBuffers(entries);
|
||
|
SetupComputeTextures(entries);
|
||
|
SetupComputeImages(entries);
|
||
|
|
||
|
buffer_cache.Unmap();
|
||
|
|
||
|
TransitionImages(sampled_views, vk::PipelineStageFlagBits::eComputeShader,
|
||
|
vk::AccessFlagBits::eShaderRead);
|
||
|
TransitionImages(image_views, vk::PipelineStageFlagBits::eComputeShader,
|
||
|
vk::AccessFlagBits::eShaderRead | vk::AccessFlagBits::eShaderWrite);
|
||
|
|
||
|
if (device.IsNvDeviceDiagnosticCheckpoints()) {
|
||
|
scheduler.Record(
|
||
|
[&pipeline](auto cmdbuf, auto& dld) { cmdbuf.setCheckpointNV(nullptr, dld); });
|
||
|
}
|
||
|
|
||
|
scheduler.Record([grid_x = launch_desc.grid_dim_x, grid_y = launch_desc.grid_dim_y,
|
||
|
grid_z = launch_desc.grid_dim_z, pipeline_handle = pipeline.GetHandle(),
|
||
|
layout = pipeline.GetLayout(),
|
||
|
descriptor_set = pipeline.CommitDescriptorSet()](auto cmdbuf, auto& dld) {
|
||
|
cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, pipeline_handle, dld);
|
||
|
cmdbuf.bindDescriptorSets(vk::PipelineBindPoint::eCompute, layout, DESCRIPTOR_SET, 1,
|
||
|
&descriptor_set, 0, nullptr, dld);
|
||
|
cmdbuf.dispatch(grid_x, grid_y, grid_z, dld);
|
||
|
});
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::FlushAll() {}
|
||
|
|
||
|
void RasterizerVulkan::FlushRegion(CacheAddr addr, u64 size) {
|
||
|
texture_cache.FlushRegion(addr, size);
|
||
|
buffer_cache.FlushRegion(addr, size);
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::InvalidateRegion(CacheAddr addr, u64 size) {
|
||
|
texture_cache.InvalidateRegion(addr, size);
|
||
|
pipeline_cache.InvalidateRegion(addr, size);
|
||
|
buffer_cache.InvalidateRegion(addr, size);
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::FlushAndInvalidateRegion(CacheAddr addr, u64 size) {
|
||
|
FlushRegion(addr, size);
|
||
|
InvalidateRegion(addr, size);
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::FlushCommands() {
|
||
|
if (draw_counter > 0) {
|
||
|
draw_counter = 0;
|
||
|
scheduler.Flush();
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::TickFrame() {
|
||
|
draw_counter = 0;
|
||
|
update_descriptor_queue.TickFrame();
|
||
|
buffer_cache.TickFrame();
|
||
|
staging_pool.TickFrame();
|
||
|
}
|
||
|
|
||
|
bool RasterizerVulkan::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Regs::Surface& src,
|
||
|
const Tegra::Engines::Fermi2D::Regs::Surface& dst,
|
||
|
const Tegra::Engines::Fermi2D::Config& copy_config) {
|
||
|
texture_cache.DoFermiCopy(src, dst, copy_config);
|
||
|
return true;
|
||
|
}
|
||
|
|
||
|
bool RasterizerVulkan::AccelerateDisplay(const Tegra::FramebufferConfig& config,
|
||
|
VAddr framebuffer_addr, u32 pixel_stride) {
|
||
|
if (!framebuffer_addr) {
|
||
|
return false;
|
||
|
}
|
||
|
|
||
|
const u8* host_ptr{system.Memory().GetPointer(framebuffer_addr)};
|
||
|
const auto surface{texture_cache.TryFindFramebufferSurface(host_ptr)};
|
||
|
if (!surface) {
|
||
|
return false;
|
||
|
}
|
||
|
|
||
|
// Verify that the cached surface is the same size and format as the requested framebuffer
|
||
|
const auto& params{surface->GetSurfaceParams()};
|
||
|
const auto& pixel_format{
|
||
|
VideoCore::Surface::PixelFormatFromGPUPixelFormat(config.pixel_format)};
|
||
|
ASSERT_MSG(params.width == config.width, "Framebuffer width is different");
|
||
|
ASSERT_MSG(params.height == config.height, "Framebuffer height is different");
|
||
|
// ASSERT_MSG(params.pixel_format == pixel_format, "Framebuffer pixel_format is different");
|
||
|
|
||
|
screen_info.image = &surface->GetImage();
|
||
|
screen_info.width = params.width;
|
||
|
screen_info.height = params.height;
|
||
|
screen_info.is_srgb = surface->GetSurfaceParams().srgb_conversion;
|
||
|
return true;
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::FlushWork() {
|
||
|
if ((++draw_counter & 7) != 7) {
|
||
|
return;
|
||
|
}
|
||
|
if (draw_counter < 4096) {
|
||
|
// Flush work to the worker thread every 8 draws
|
||
|
scheduler.DispatchWork();
|
||
|
} else {
|
||
|
// Flush work to the GPU (and implicitly the worker thread) every N draws
|
||
|
scheduler.Flush();
|
||
|
draw_counter = 0;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
RasterizerVulkan::Texceptions RasterizerVulkan::UpdateAttachments() {
|
||
|
MICROPROFILE_SCOPE(Vulkan_RenderTargets);
|
||
|
auto& dirty = system.GPU().Maxwell3D().dirty;
|
||
|
const bool update_rendertargets = dirty.render_settings;
|
||
|
dirty.render_settings = false;
|
||
|
|
||
|
texture_cache.GuardRenderTargets(true);
|
||
|
|
||
|
Texceptions texceptions;
|
||
|
for (std::size_t rt = 0; rt < Maxwell::NumRenderTargets; ++rt) {
|
||
|
if (update_rendertargets) {
|
||
|
color_attachments[rt] = texture_cache.GetColorBufferSurface(rt, true);
|
||
|
}
|
||
|
if (color_attachments[rt] && WalkAttachmentOverlaps(*color_attachments[rt])) {
|
||
|
texceptions.set(rt);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (update_rendertargets) {
|
||
|
zeta_attachment = texture_cache.GetDepthBufferSurface(true);
|
||
|
}
|
||
|
if (zeta_attachment && WalkAttachmentOverlaps(*zeta_attachment)) {
|
||
|
texceptions.set(ZETA_TEXCEPTION_INDEX);
|
||
|
}
|
||
|
|
||
|
texture_cache.GuardRenderTargets(false);
|
||
|
|
||
|
return texceptions;
|
||
|
}
|
||
|
|
||
|
bool RasterizerVulkan::WalkAttachmentOverlaps(const CachedSurfaceView& attachment) {
|
||
|
bool overlap = false;
|
||
|
for (auto& [view, layout] : sampled_views) {
|
||
|
if (!attachment.IsSameSurface(*view)) {
|
||
|
continue;
|
||
|
}
|
||
|
overlap = true;
|
||
|
*layout = vk::ImageLayout::eGeneral;
|
||
|
}
|
||
|
return overlap;
|
||
|
}
|
||
|
|
||
|
std::tuple<vk::Framebuffer, vk::Extent2D> RasterizerVulkan::ConfigureFramebuffers(
|
||
|
vk::RenderPass renderpass) {
|
||
|
FramebufferCacheKey fbkey;
|
||
|
fbkey.renderpass = renderpass;
|
||
|
fbkey.width = std::numeric_limits<u32>::max();
|
||
|
fbkey.height = std::numeric_limits<u32>::max();
|
||
|
|
||
|
const auto MarkAsModifiedAndPush = [&](const View& view) {
|
||
|
if (view == nullptr) {
|
||
|
return false;
|
||
|
}
|
||
|
fbkey.views.push_back(view->GetHandle());
|
||
|
fbkey.width = std::min(fbkey.width, view->GetWidth());
|
||
|
fbkey.height = std::min(fbkey.height, view->GetHeight());
|
||
|
return true;
|
||
|
};
|
||
|
|
||
|
for (std::size_t index = 0; index < std::size(color_attachments); ++index) {
|
||
|
if (MarkAsModifiedAndPush(color_attachments[index])) {
|
||
|
texture_cache.MarkColorBufferInUse(index);
|
||
|
}
|
||
|
}
|
||
|
if (MarkAsModifiedAndPush(zeta_attachment)) {
|
||
|
texture_cache.MarkDepthBufferInUse();
|
||
|
}
|
||
|
|
||
|
const auto [fbentry, is_cache_miss] = framebuffer_cache.try_emplace(fbkey);
|
||
|
auto& framebuffer = fbentry->second;
|
||
|
if (is_cache_miss) {
|
||
|
const vk::FramebufferCreateInfo framebuffer_ci(
|
||
|
{}, fbkey.renderpass, static_cast<u32>(fbkey.views.size()), fbkey.views.data(),
|
||
|
fbkey.width, fbkey.height, 1);
|
||
|
const auto dev = device.GetLogical();
|
||
|
const auto& dld = device.GetDispatchLoader();
|
||
|
framebuffer = dev.createFramebufferUnique(framebuffer_ci, nullptr, dld);
|
||
|
}
|
||
|
|
||
|
return {*framebuffer, vk::Extent2D{fbkey.width, fbkey.height}};
|
||
|
}
|
||
|
|
||
|
RasterizerVulkan::DrawParameters RasterizerVulkan::SetupGeometry(FixedPipelineState& fixed_state,
|
||
|
BufferBindings& buffer_bindings,
|
||
|
bool is_indexed,
|
||
|
bool is_instanced) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_Geometry);
|
||
|
|
||
|
const auto& gpu = system.GPU().Maxwell3D();
|
||
|
const auto& regs = gpu.regs;
|
||
|
|
||
|
SetupVertexArrays(fixed_state.vertex_input, buffer_bindings);
|
||
|
|
||
|
const u32 base_instance = regs.vb_base_instance;
|
||
|
const u32 num_instances = is_instanced ? gpu.mme_draw.instance_count : 1;
|
||
|
const u32 base_vertex = is_indexed ? regs.vb_element_base : regs.vertex_buffer.first;
|
||
|
const u32 num_vertices = is_indexed ? regs.index_array.count : regs.vertex_buffer.count;
|
||
|
|
||
|
DrawParameters params{base_instance, num_instances, base_vertex, num_vertices, is_indexed};
|
||
|
SetupIndexBuffer(buffer_bindings, params, is_indexed);
|
||
|
|
||
|
return params;
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupShaderDescriptors(
|
||
|
const std::array<Shader, Maxwell::MaxShaderProgram>& shaders) {
|
||
|
texture_cache.GuardSamplers(true);
|
||
|
|
||
|
for (std::size_t stage = 0; stage < Maxwell::MaxShaderStage; ++stage) {
|
||
|
// Skip VertexA stage
|
||
|
const auto& shader = shaders[stage + 1];
|
||
|
if (!shader) {
|
||
|
continue;
|
||
|
}
|
||
|
const auto& entries = shader->GetEntries();
|
||
|
SetupGraphicsConstBuffers(entries, stage);
|
||
|
SetupGraphicsGlobalBuffers(entries, stage);
|
||
|
SetupGraphicsTexelBuffers(entries, stage);
|
||
|
SetupGraphicsTextures(entries, stage);
|
||
|
SetupGraphicsImages(entries, stage);
|
||
|
}
|
||
|
texture_cache.GuardSamplers(false);
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupImageTransitions(
|
||
|
Texceptions texceptions, const std::array<View, Maxwell::NumRenderTargets>& color_attachments,
|
||
|
const View& zeta_attachment) {
|
||
|
TransitionImages(sampled_views, vk::PipelineStageFlagBits::eAllGraphics,
|
||
|
vk::AccessFlagBits::eShaderRead);
|
||
|
TransitionImages(image_views, vk::PipelineStageFlagBits::eAllGraphics,
|
||
|
vk::AccessFlagBits::eShaderRead | vk::AccessFlagBits::eShaderWrite);
|
||
|
|
||
|
for (std::size_t rt = 0; rt < std::size(color_attachments); ++rt) {
|
||
|
const auto color_attachment = color_attachments[rt];
|
||
|
if (color_attachment == nullptr) {
|
||
|
continue;
|
||
|
}
|
||
|
const auto image_layout =
|
||
|
texceptions[rt] ? vk::ImageLayout::eGeneral : vk::ImageLayout::eColorAttachmentOptimal;
|
||
|
color_attachment->Transition(
|
||
|
image_layout, vk::PipelineStageFlagBits::eColorAttachmentOutput,
|
||
|
vk::AccessFlagBits::eColorAttachmentRead | vk::AccessFlagBits::eColorAttachmentWrite);
|
||
|
}
|
||
|
|
||
|
if (zeta_attachment != nullptr) {
|
||
|
const auto image_layout = texceptions[ZETA_TEXCEPTION_INDEX]
|
||
|
? vk::ImageLayout::eGeneral
|
||
|
: vk::ImageLayout::eDepthStencilAttachmentOptimal;
|
||
|
zeta_attachment->Transition(image_layout, vk::PipelineStageFlagBits::eLateFragmentTests,
|
||
|
vk::AccessFlagBits::eDepthStencilAttachmentRead |
|
||
|
vk::AccessFlagBits::eDepthStencilAttachmentWrite);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::UpdateDynamicStates() {
|
||
|
auto& gpu = system.GPU().Maxwell3D();
|
||
|
UpdateViewportsState(gpu);
|
||
|
UpdateScissorsState(gpu);
|
||
|
UpdateDepthBias(gpu);
|
||
|
UpdateBlendConstants(gpu);
|
||
|
UpdateDepthBounds(gpu);
|
||
|
UpdateStencilFaces(gpu);
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupVertexArrays(FixedPipelineState::VertexInput& vertex_input,
|
||
|
BufferBindings& buffer_bindings) {
|
||
|
const auto& regs = system.GPU().Maxwell3D().regs;
|
||
|
|
||
|
for (u32 index = 0; index < static_cast<u32>(Maxwell::NumVertexAttributes); ++index) {
|
||
|
const auto& attrib = regs.vertex_attrib_format[index];
|
||
|
if (!attrib.IsValid()) {
|
||
|
continue;
|
||
|
}
|
||
|
|
||
|
const auto& buffer = regs.vertex_array[attrib.buffer];
|
||
|
ASSERT(buffer.IsEnabled());
|
||
|
|
||
|
vertex_input.attributes[vertex_input.num_attributes++] =
|
||
|
FixedPipelineState::VertexAttribute(index, attrib.buffer, attrib.type, attrib.size,
|
||
|
attrib.offset);
|
||
|
}
|
||
|
|
||
|
for (u32 index = 0; index < static_cast<u32>(Maxwell::NumVertexArrays); ++index) {
|
||
|
const auto& vertex_array = regs.vertex_array[index];
|
||
|
if (!vertex_array.IsEnabled()) {
|
||
|
continue;
|
||
|
}
|
||
|
|
||
|
const GPUVAddr start{vertex_array.StartAddress()};
|
||
|
const GPUVAddr end{regs.vertex_array_limit[index].LimitAddress()};
|
||
|
|
||
|
ASSERT(end > start);
|
||
|
const std::size_t size{end - start + 1};
|
||
|
const auto [buffer, offset] = buffer_cache.UploadMemory(start, size);
|
||
|
|
||
|
vertex_input.bindings[vertex_input.num_bindings++] = FixedPipelineState::VertexBinding(
|
||
|
index, vertex_array.stride,
|
||
|
regs.instanced_arrays.IsInstancingEnabled(index) ? vertex_array.divisor : 0);
|
||
|
buffer_bindings.AddVertexBinding(buffer, offset);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupIndexBuffer(BufferBindings& buffer_bindings, DrawParameters& params,
|
||
|
bool is_indexed) {
|
||
|
const auto& regs = system.GPU().Maxwell3D().regs;
|
||
|
switch (regs.draw.topology) {
|
||
|
case Maxwell::PrimitiveTopology::Quads:
|
||
|
if (params.is_indexed) {
|
||
|
UNIMPLEMENTED();
|
||
|
} else {
|
||
|
const auto [buffer, offset] =
|
||
|
quad_array_pass.Assemble(params.num_vertices, params.base_vertex);
|
||
|
buffer_bindings.SetIndexBinding(&buffer, offset, vk::IndexType::eUint32);
|
||
|
params.base_vertex = 0;
|
||
|
params.num_vertices = params.num_vertices * 6 / 4;
|
||
|
params.is_indexed = true;
|
||
|
}
|
||
|
break;
|
||
|
default: {
|
||
|
if (!is_indexed) {
|
||
|
break;
|
||
|
}
|
||
|
auto [buffer, offset] =
|
||
|
buffer_cache.UploadMemory(regs.index_array.IndexStart(), CalculateIndexBufferSize());
|
||
|
|
||
|
auto format = regs.index_array.format;
|
||
|
const bool is_uint8 = format == Maxwell::IndexFormat::UnsignedByte;
|
||
|
if (is_uint8 && !device.IsExtIndexTypeUint8Supported()) {
|
||
|
std::tie(buffer, offset) = uint8_pass.Assemble(params.num_vertices, *buffer, offset);
|
||
|
format = Maxwell::IndexFormat::UnsignedShort;
|
||
|
}
|
||
|
|
||
|
buffer_bindings.SetIndexBinding(buffer, offset, MaxwellToVK::IndexFormat(device, format));
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupGraphicsConstBuffers(const ShaderEntries& entries, std::size_t stage) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_ConstBuffers);
|
||
|
const auto& gpu = system.GPU().Maxwell3D();
|
||
|
const auto& shader_stage = gpu.state.shader_stages[stage];
|
||
|
for (const auto& entry : entries.const_buffers) {
|
||
|
SetupConstBuffer(entry, shader_stage.const_buffers[entry.GetIndex()]);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupGraphicsGlobalBuffers(const ShaderEntries& entries, std::size_t stage) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_GlobalBuffers);
|
||
|
auto& gpu{system.GPU()};
|
||
|
const auto cbufs{gpu.Maxwell3D().state.shader_stages[stage]};
|
||
|
|
||
|
for (const auto& entry : entries.global_buffers) {
|
||
|
const auto addr = cbufs.const_buffers[entry.GetCbufIndex()].address + entry.GetCbufOffset();
|
||
|
SetupGlobalBuffer(entry, addr);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupGraphicsTexelBuffers(const ShaderEntries& entries, std::size_t stage) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_Textures);
|
||
|
const auto& gpu = system.GPU().Maxwell3D();
|
||
|
for (const auto& entry : entries.texel_buffers) {
|
||
|
const auto image = GetTextureInfo(gpu, entry, stage).tic;
|
||
|
SetupTexelBuffer(image, entry);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupGraphicsTextures(const ShaderEntries& entries, std::size_t stage) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_Textures);
|
||
|
const auto& gpu = system.GPU().Maxwell3D();
|
||
|
for (const auto& entry : entries.samplers) {
|
||
|
const auto texture = GetTextureInfo(gpu, entry, stage);
|
||
|
SetupTexture(texture, entry);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupGraphicsImages(const ShaderEntries& entries, std::size_t stage) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_Images);
|
||
|
const auto& gpu = system.GPU().KeplerCompute();
|
||
|
for (const auto& entry : entries.images) {
|
||
|
const auto tic = GetTextureInfo(gpu, entry, stage).tic;
|
||
|
SetupImage(tic, entry);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupComputeConstBuffers(const ShaderEntries& entries) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_ConstBuffers);
|
||
|
const auto& launch_desc = system.GPU().KeplerCompute().launch_description;
|
||
|
for (const auto& entry : entries.const_buffers) {
|
||
|
const auto& config = launch_desc.const_buffer_config[entry.GetIndex()];
|
||
|
const std::bitset<8> mask = launch_desc.const_buffer_enable_mask.Value();
|
||
|
Tegra::Engines::ConstBufferInfo buffer;
|
||
|
buffer.address = config.Address();
|
||
|
buffer.size = config.size;
|
||
|
buffer.enabled = mask[entry.GetIndex()];
|
||
|
SetupConstBuffer(entry, buffer);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupComputeGlobalBuffers(const ShaderEntries& entries) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_GlobalBuffers);
|
||
|
const auto cbufs{system.GPU().KeplerCompute().launch_description.const_buffer_config};
|
||
|
for (const auto& entry : entries.global_buffers) {
|
||
|
const auto addr{cbufs[entry.GetCbufIndex()].Address() + entry.GetCbufOffset()};
|
||
|
SetupGlobalBuffer(entry, addr);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupComputeTexelBuffers(const ShaderEntries& entries) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_Textures);
|
||
|
const auto& gpu = system.GPU().KeplerCompute();
|
||
|
for (const auto& entry : entries.texel_buffers) {
|
||
|
const auto image = GetTextureInfo(gpu, entry, ComputeShaderIndex).tic;
|
||
|
SetupTexelBuffer(image, entry);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupComputeTextures(const ShaderEntries& entries) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_Textures);
|
||
|
const auto& gpu = system.GPU().KeplerCompute();
|
||
|
for (const auto& entry : entries.samplers) {
|
||
|
const auto texture = GetTextureInfo(gpu, entry, ComputeShaderIndex);
|
||
|
SetupTexture(texture, entry);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupComputeImages(const ShaderEntries& entries) {
|
||
|
MICROPROFILE_SCOPE(Vulkan_Images);
|
||
|
const auto& gpu = system.GPU().KeplerCompute();
|
||
|
for (const auto& entry : entries.images) {
|
||
|
const auto tic = GetTextureInfo(gpu, entry, ComputeShaderIndex).tic;
|
||
|
SetupImage(tic, entry);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupConstBuffer(const ConstBufferEntry& entry,
|
||
|
const Tegra::Engines::ConstBufferInfo& buffer) {
|
||
|
// Align the size to avoid bad std140 interactions
|
||
|
const std::size_t size =
|
||
|
Common::AlignUp(CalculateConstBufferSize(entry, buffer), 4 * sizeof(float));
|
||
|
ASSERT(size <= MaxConstbufferSize);
|
||
|
|
||
|
const auto [buffer_handle, offset] =
|
||
|
buffer_cache.UploadMemory(buffer.address, size, device.GetUniformBufferAlignment());
|
||
|
|
||
|
update_descriptor_queue.AddBuffer(buffer_handle, offset, size);
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupGlobalBuffer(const GlobalBufferEntry& entry, GPUVAddr address) {
|
||
|
auto& memory_manager{system.GPU().MemoryManager()};
|
||
|
const auto actual_addr = memory_manager.Read<u64>(address);
|
||
|
const auto size = memory_manager.Read<u32>(address + 8);
|
||
|
|
||
|
if (size == 0) {
|
||
|
// Sometimes global memory pointers don't have a proper size. Upload a dummy entry because
|
||
|
// Vulkan doesn't like empty buffers.
|
||
|
constexpr std::size_t dummy_size = 4;
|
||
|
const auto buffer = buffer_cache.GetEmptyBuffer(dummy_size);
|
||
|
update_descriptor_queue.AddBuffer(buffer, 0, dummy_size);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
const auto [buffer, offset] = buffer_cache.UploadMemory(
|
||
|
actual_addr, size, device.GetStorageBufferAlignment(), entry.IsWritten());
|
||
|
update_descriptor_queue.AddBuffer(buffer, offset, size);
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupTexelBuffer(const Tegra::Texture::TICEntry& tic,
|
||
|
const TexelBufferEntry& entry) {
|
||
|
auto view = texture_cache.GetTextureSurface(tic, entry);
|
||
|
ASSERT(view->IsBufferView());
|
||
|
|
||
|
update_descriptor_queue.AddTexelBuffer(view->GetBufferView());
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupTexture(const Tegra::Texture::FullTextureInfo& texture,
|
||
|
const SamplerEntry& entry) {
|
||
|
auto view = texture_cache.GetTextureSurface(texture.tic, entry);
|
||
|
ASSERT(!view->IsBufferView());
|
||
|
|
||
|
const auto image_view = view->GetHandle(texture.tic.x_source, texture.tic.y_source,
|
||
|
texture.tic.z_source, texture.tic.w_source);
|
||
|
const auto sampler = sampler_cache.GetSampler(texture.tsc);
|
||
|
update_descriptor_queue.AddSampledImage(sampler, image_view);
|
||
|
|
||
|
const auto image_layout = update_descriptor_queue.GetLastImageLayout();
|
||
|
*image_layout = vk::ImageLayout::eShaderReadOnlyOptimal;
|
||
|
sampled_views.push_back(ImageView{std::move(view), image_layout});
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::SetupImage(const Tegra::Texture::TICEntry& tic, const ImageEntry& entry) {
|
||
|
auto view = texture_cache.GetImageSurface(tic, entry);
|
||
|
|
||
|
if (entry.IsWritten()) {
|
||
|
view->MarkAsModified(texture_cache.Tick());
|
||
|
}
|
||
|
|
||
|
UNIMPLEMENTED_IF(tic.IsBuffer());
|
||
|
|
||
|
const auto image_view = view->GetHandle(tic.x_source, tic.y_source, tic.z_source, tic.w_source);
|
||
|
update_descriptor_queue.AddImage(image_view);
|
||
|
|
||
|
const auto image_layout = update_descriptor_queue.GetLastImageLayout();
|
||
|
*image_layout = vk::ImageLayout::eGeneral;
|
||
|
image_views.push_back(ImageView{std::move(view), image_layout});
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::UpdateViewportsState(Tegra::Engines::Maxwell3D& gpu) {
|
||
|
if (!gpu.dirty.viewport_transform && scheduler.TouchViewports()) {
|
||
|
return;
|
||
|
}
|
||
|
gpu.dirty.viewport_transform = false;
|
||
|
const auto& regs = gpu.regs;
|
||
|
const std::array viewports{
|
||
|
GetViewportState(device, regs, 0), GetViewportState(device, regs, 1),
|
||
|
GetViewportState(device, regs, 2), GetViewportState(device, regs, 3),
|
||
|
GetViewportState(device, regs, 4), GetViewportState(device, regs, 5),
|
||
|
GetViewportState(device, regs, 6), GetViewportState(device, regs, 7),
|
||
|
GetViewportState(device, regs, 8), GetViewportState(device, regs, 9),
|
||
|
GetViewportState(device, regs, 10), GetViewportState(device, regs, 11),
|
||
|
GetViewportState(device, regs, 12), GetViewportState(device, regs, 13),
|
||
|
GetViewportState(device, regs, 14), GetViewportState(device, regs, 15)};
|
||
|
scheduler.Record([viewports](auto cmdbuf, auto& dld) {
|
||
|
cmdbuf.setViewport(0, static_cast<u32>(viewports.size()), viewports.data(), dld);
|
||
|
});
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::UpdateScissorsState(Tegra::Engines::Maxwell3D& gpu) {
|
||
|
if (!gpu.dirty.scissor_test && scheduler.TouchScissors()) {
|
||
|
return;
|
||
|
}
|
||
|
gpu.dirty.scissor_test = false;
|
||
|
const auto& regs = gpu.regs;
|
||
|
const std::array scissors = {
|
||
|
GetScissorState(regs, 0), GetScissorState(regs, 1), GetScissorState(regs, 2),
|
||
|
GetScissorState(regs, 3), GetScissorState(regs, 4), GetScissorState(regs, 5),
|
||
|
GetScissorState(regs, 6), GetScissorState(regs, 7), GetScissorState(regs, 8),
|
||
|
GetScissorState(regs, 9), GetScissorState(regs, 10), GetScissorState(regs, 11),
|
||
|
GetScissorState(regs, 12), GetScissorState(regs, 13), GetScissorState(regs, 14),
|
||
|
GetScissorState(regs, 15)};
|
||
|
scheduler.Record([scissors](auto cmdbuf, auto& dld) {
|
||
|
cmdbuf.setScissor(0, static_cast<u32>(scissors.size()), scissors.data(), dld);
|
||
|
});
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::UpdateDepthBias(Tegra::Engines::Maxwell3D& gpu) {
|
||
|
if (!gpu.dirty.polygon_offset && scheduler.TouchDepthBias()) {
|
||
|
return;
|
||
|
}
|
||
|
gpu.dirty.polygon_offset = false;
|
||
|
const auto& regs = gpu.regs;
|
||
|
scheduler.Record([constant = regs.polygon_offset_units, clamp = regs.polygon_offset_clamp,
|
||
|
factor = regs.polygon_offset_factor](auto cmdbuf, auto& dld) {
|
||
|
cmdbuf.setDepthBias(constant, clamp, factor / 2.0f, dld);
|
||
|
});
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::UpdateBlendConstants(Tegra::Engines::Maxwell3D& gpu) {
|
||
|
if (!gpu.dirty.blend_state && scheduler.TouchBlendConstants()) {
|
||
|
return;
|
||
|
}
|
||
|
gpu.dirty.blend_state = false;
|
||
|
const std::array blend_color = {gpu.regs.blend_color.r, gpu.regs.blend_color.g,
|
||
|
gpu.regs.blend_color.b, gpu.regs.blend_color.a};
|
||
|
scheduler.Record([blend_color](auto cmdbuf, auto& dld) {
|
||
|
cmdbuf.setBlendConstants(blend_color.data(), dld);
|
||
|
});
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::UpdateDepthBounds(Tegra::Engines::Maxwell3D& gpu) {
|
||
|
if (!gpu.dirty.depth_bounds_values && scheduler.TouchDepthBounds()) {
|
||
|
return;
|
||
|
}
|
||
|
gpu.dirty.depth_bounds_values = false;
|
||
|
const auto& regs = gpu.regs;
|
||
|
scheduler.Record([min = regs.depth_bounds[0], max = regs.depth_bounds[1]](
|
||
|
auto cmdbuf, auto& dld) { cmdbuf.setDepthBounds(min, max, dld); });
|
||
|
}
|
||
|
|
||
|
void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D& gpu) {
|
||
|
if (!gpu.dirty.stencil_test && scheduler.TouchStencilValues()) {
|
||
|
return;
|
||
|
}
|
||
|
gpu.dirty.stencil_test = false;
|
||
|
const auto& regs = gpu.regs;
|
||
|
if (regs.stencil_two_side_enable) {
|
||
|
// Separate values per face
|
||
|
scheduler.Record(
|
||
|
[front_ref = regs.stencil_front_func_ref, front_write_mask = regs.stencil_front_mask,
|
||
|
front_test_mask = regs.stencil_front_func_mask, back_ref = regs.stencil_back_func_ref,
|
||
|
back_write_mask = regs.stencil_back_mask,
|
||
|
back_test_mask = regs.stencil_back_func_mask](auto cmdbuf, auto& dld) {
|
||
|
// Front face
|
||
|
cmdbuf.setStencilReference(vk::StencilFaceFlagBits::eFront, front_ref, dld);
|
||
|
cmdbuf.setStencilWriteMask(vk::StencilFaceFlagBits::eFront, front_write_mask, dld);
|
||
|
cmdbuf.setStencilCompareMask(vk::StencilFaceFlagBits::eFront, front_test_mask, dld);
|
||
|
|
||
|
// Back face
|
||
|
cmdbuf.setStencilReference(vk::StencilFaceFlagBits::eBack, back_ref, dld);
|
||
|
cmdbuf.setStencilWriteMask(vk::StencilFaceFlagBits::eBack, back_write_mask, dld);
|
||
|
cmdbuf.setStencilCompareMask(vk::StencilFaceFlagBits::eBack, back_test_mask, dld);
|
||
|
});
|
||
|
} else {
|
||
|
// Front face defines both faces
|
||
|
scheduler.Record([ref = regs.stencil_back_func_ref, write_mask = regs.stencil_back_mask,
|
||
|
test_mask = regs.stencil_back_func_mask](auto cmdbuf, auto& dld) {
|
||
|
cmdbuf.setStencilReference(vk::StencilFaceFlagBits::eFrontAndBack, ref, dld);
|
||
|
cmdbuf.setStencilWriteMask(vk::StencilFaceFlagBits::eFrontAndBack, write_mask, dld);
|
||
|
cmdbuf.setStencilCompareMask(vk::StencilFaceFlagBits::eFrontAndBack, test_mask, dld);
|
||
|
});
|
||
|
}
|
||
|
}
|
||
|
|
||
|
std::size_t RasterizerVulkan::CalculateGraphicsStreamBufferSize(bool is_indexed) const {
|
||
|
std::size_t size = CalculateVertexArraysSize();
|
||
|
if (is_indexed) {
|
||
|
size = Common::AlignUp(size, 4) + CalculateIndexBufferSize();
|
||
|
}
|
||
|
size += Maxwell::MaxConstBuffers * (MaxConstbufferSize + device.GetUniformBufferAlignment());
|
||
|
return size;
|
||
|
}
|
||
|
|
||
|
std::size_t RasterizerVulkan::CalculateComputeStreamBufferSize() const {
|
||
|
return Tegra::Engines::KeplerCompute::NumConstBuffers *
|
||
|
(Maxwell::MaxConstBufferSize + device.GetUniformBufferAlignment());
|
||
|
}
|
||
|
|
||
|
std::size_t RasterizerVulkan::CalculateVertexArraysSize() const {
|
||
|
const auto& regs = system.GPU().Maxwell3D().regs;
|
||
|
|
||
|
std::size_t size = 0;
|
||
|
for (u32 index = 0; index < Maxwell::NumVertexArrays; ++index) {
|
||
|
// This implementation assumes that all attributes are used in the shader.
|
||
|
const GPUVAddr start{regs.vertex_array[index].StartAddress()};
|
||
|
const GPUVAddr end{regs.vertex_array_limit[index].LimitAddress()};
|
||
|
DEBUG_ASSERT(end > start);
|
||
|
|
||
|
size += (end - start + 1) * regs.vertex_array[index].enable;
|
||
|
}
|
||
|
return size;
|
||
|
}
|
||
|
|
||
|
std::size_t RasterizerVulkan::CalculateIndexBufferSize() const {
|
||
|
const auto& regs = system.GPU().Maxwell3D().regs;
|
||
|
return static_cast<std::size_t>(regs.index_array.count) *
|
||
|
static_cast<std::size_t>(regs.index_array.FormatSizeInBytes());
|
||
|
}
|
||
|
|
||
|
std::size_t RasterizerVulkan::CalculateConstBufferSize(
|
||
|
const ConstBufferEntry& entry, const Tegra::Engines::ConstBufferInfo& buffer) const {
|
||
|
if (entry.IsIndirect()) {
|
||
|
// Buffer is accessed indirectly, so upload the entire thing
|
||
|
return buffer.size;
|
||
|
} else {
|
||
|
// Buffer is accessed directly, upload just what we use
|
||
|
return entry.GetSize();
|
||
|
}
|
||
|
}
|
||
|
|
||
|
RenderPassParams RasterizerVulkan::GetRenderPassParams(Texceptions texceptions) const {
|
||
|
using namespace VideoCore::Surface;
|
||
|
|
||
|
const auto& regs = system.GPU().Maxwell3D().regs;
|
||
|
RenderPassParams renderpass_params;
|
||
|
|
||
|
for (std::size_t rt = 0; rt < static_cast<std::size_t>(regs.rt_control.count); ++rt) {
|
||
|
const auto& rendertarget = regs.rt[rt];
|
||
|
if (rendertarget.Address() == 0 || rendertarget.format == Tegra::RenderTargetFormat::NONE)
|
||
|
continue;
|
||
|
renderpass_params.color_attachments.push_back(RenderPassParams::ColorAttachment{
|
||
|
static_cast<u32>(rt), PixelFormatFromRenderTargetFormat(rendertarget.format),
|
||
|
texceptions.test(rt)});
|
||
|
}
|
||
|
|
||
|
renderpass_params.has_zeta = regs.zeta_enable;
|
||
|
if (renderpass_params.has_zeta) {
|
||
|
renderpass_params.zeta_pixel_format = PixelFormatFromDepthFormat(regs.zeta.format);
|
||
|
renderpass_params.zeta_texception = texceptions[ZETA_TEXCEPTION_INDEX];
|
||
|
}
|
||
|
|
||
|
return renderpass_params;
|
||
|
}
|
||
|
|
||
|
} // namespace Vulkan
|