bunnei
f34176996e
Merge pull request #6385 from degasus/save_memory_access
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core/memory: Check our memory fallbacks for out-of-bound behavior.
2021-05-30 23:21:39 -07:00
Markus Wick
ddb186e61d
core/arm_interface: Improve the performance of memory fallbacks.
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We just create one memory subsystem. This is a constant all the time.
So there is no need to call the non-inlined parent.Memory() helper on every callback.
2021-05-29 09:02:19 +02:00
Markus Wick
d2d7a5060f
externals: Update dynarmic.
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The new version supports fastmem on a64.
2021-05-29 08:53:01 +02:00
Markus Wick
3d2e80daed
core/arm_interface: Call SVC after end of dynarmic block.
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So we can modify all of dynarmic states within SVC without ExceptionalExit.
Especially as the ExceptionalExit hack is dropped on upstream dynarmic.
2021-05-27 23:23:23 +02:00
Markus Wick
993dbe49fc
core/arm: Drop ChangeProcessorID.
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This code was used to switch the CPU ID on thread switches.
However since "hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.", the CPU ID is not a constant.
This has been dead code since this rewrite, and dropped in dynarmic as well. So there is no need to keep it.
2021-05-26 19:48:24 +02:00
bunnei
7626ca3343
Merge pull request #6321 from lat9nq/per-game-cpu
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configuration: Add CPU tab to game properties and slight per-game settings rework
2021-05-20 20:10:56 -07:00
Lioncash
9a07ed53eb
core: Make variable shadowing a compile-time error
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Now that we have most of core free of shadowing, we can enable the
warning as an error to catch anything that may be remaining and also
eliminate this class of logic bug entirely.
2021-05-16 03:43:16 -04:00
lat9nq
e169fdad4f
general: Make CPU accuracy and related a Settings::Setting
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Required to make CPU accuracy and unsafe settings available to use as a
per-game setting.
2021-05-15 20:46:48 -04:00
Lioncash
9e726a9250
service: Resolve cases of member field shadowing
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Now all that remains is for kernel code to be 'shadow-free' and then
-Wshadow can be turned into an error.
2021-05-04 04:38:38 -04:00
bunnei
a4c6712a4b
common: Move settings to common from core.
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- Removes a dependency on core and input_common from common.
2021-04-14 16:24:03 -07:00
MerryMage
0fbd7752c3
arm_dynarmic: Increase size of code cache
2021-04-02 18:09:15 +01:00
MerryMage
52dae41d7f
arm_dynarmic: Always have a 'valid' jit instance
2021-03-24 18:47:17 +00:00
bunnei
a35717b245
core: arm_dynarmic: Ensure JIT state is saved/restored on page table changes.
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- We re-create the JIT here without preserving any state.
2021-03-21 15:25:25 -07:00
MerryMage
821fc4a7b6
arm_dynarmic_32: Print out CPSR.T on exception
2021-02-01 18:35:33 +00:00
bunnei
c8fe8247ee
arm: dynarmic: Reintroduce JIT checks on SaveContext/LoadContext.
2021-01-28 21:50:39 -08:00
bunnei
055194d2ab
core: arm: Remove unnecessary JIT checks.
2021-01-28 21:42:26 -08:00
bunnei
9a4e148f9e
arm: arm_dynarmic: Skip calls when JIT is invalid.
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- This can happen if called from an idle or suspension thread.
2021-01-28 21:42:25 -08:00
ReinUsesLisp
b4451c5e81
core: Silence unhandled enum in switch warnings
2021-01-08 23:21:07 -03:00
MerryMage
57c9da1b39
dynarmic: Add Unsafe_InaccurateNaN optimization
2021-01-02 20:13:21 +00:00
ReinUsesLisp
b3587102d1
core/memory: Read and write page table atomically
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Squash attributes into the pointer's integer, making them an uintptr_t
pair containing 2 bits at the bottom and then the pointer. These bits
are currently unused thanks to alignment requirements.
Configure Dynarmic to mask out these bits on pointer reads.
While we are at it, remove some unused attributes carried over from
Citra.
Read/Write and other hot functions use a two step unpacking process that
is less readable to stop MSVC from emitting an extra AND instruction in
the hot path:
mov rdi,rcx
shr rdx,0Ch
mov r8,qword ptr [rax+8]
mov rax,qword ptr [r8+rdx*8]
mov rdx,rax
-and al,3
and rdx,0FFFFFFFFFFFFFFFCh
je Core::Memory::Memory::Impl::Read<unsigned char>
mov rax,qword ptr [vaddr]
movzx eax,byte ptr [rdx+rax]
2020-12-29 21:54:49 -03:00
bunnei
c10a37e5b6
hle: kernel: physical_core: Clear exclusive state after each run.
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- This is closer to pre-multicore behavior, and works a bit better.
2020-12-06 00:03:24 -08:00
bunnei
63fd1bb503
core: arm: Implement InvalidateCacheRange for CPU cache invalidation.
2020-11-29 01:31:52 -08:00
bunnei
7b642c7781
hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.
2020-11-29 01:31:51 -08:00
Lioncash
fc6db97a09
core: Remove usage of unicorn
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Unicorn long-since lost most of its use, due to dynarmic gaining support
for handling most instructions. At this point any further issues
encountered should be used to make dynarmic better.
This also allows us to remove our dependency on Python.
2020-11-03 20:22:05 -05:00
bunnei
3d592972dc
Revert "core: Fix clang build"
2020-10-20 19:07:39 -07:00
Lioncash
be1954e04c
core: Fix clang build
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Recent changes to the build system that made more warnings be flagged as
errors caused building via clang to break.
Fixes #4795
2020-10-17 19:50:39 -04:00
MerryMage
836ec9176a
dynarmic: Add unsafe optimizations
2020-08-16 14:15:39 +01:00
MerryMage
505aa3a4c1
configure_cpu: Show/Hide debugging options
2020-07-11 16:38:38 +01:00
MerryMage
0193202964
configuration: Add settings to enable/disable specific CPU optimizations
2020-07-11 14:34:09 +01:00
Fernando Sahmkow
2f8947583f
Core/Common: Address Feedback.
2020-06-27 18:20:06 -04:00
Fernando Sahmkow
4105f38022
SVC: Implement 32-bits wrappers and update Dynarmic.
2020-06-27 11:36:27 -04:00
Fernando Sahmkow
b8df61c642
ARM: Update Dynarmic and Setup A32 according to latest interface.
2020-06-27 11:36:26 -04:00
Fernando Sahmkow
0a8013d71e
ARMDynarmicInterface: Correct GCC Build Errors.
2020-06-27 11:36:17 -04:00
Fernando Sahmkow
7b44187fd2
Dynarmic Interface: don't clear cache if JIT has not been created.
2020-06-27 11:36:08 -04:00
Fernando Sahmkow
48fa3b7a0f
General: Cleanup legacy code.
2020-06-27 11:36:05 -04:00
Fernando Sahmkow
f5e32935ca
SingleCore: Use Cycle Timing instead of Host Timing.
2020-06-27 11:36:01 -04:00
Fernando Sahmkow
1567824d2d
General: Move ARM_Interface into Threads.
2020-06-27 11:35:58 -04:00
Fernando Sahmkow
1b82ccec22
Core: Refactor ARM Interface.
2020-06-27 11:35:56 -04:00
Fernando Sahmkow
87c49aa7be
SVC/ARM: Correct svcSendSyncRequest and cache ticks on arm interface.
2020-06-27 11:35:53 -04:00
Fernando Sahmkow
7020d498c5
General: Fix microprofile on dynarmic/svc, fix wait tree showing which threads were running.
2020-06-27 11:35:48 -04:00
Fernando Sahmkow
a33fbaddec
Core: Correct rebase.
2020-06-27 11:35:29 -04:00
Fernando Sahmkow
e31425df38
General: Recover Prometheus project from harddrive failure
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This commit: Implements CPU Interrupts, Replaces Cycle Timing for Host
Timing, Reworks the Kernel's Scheduler, Introduce Idle State and
Suspended State, Recreates the bootmanager, Initializes Multicore
system.
2020-06-27 11:35:06 -04:00
Morph
e0af4cdf98
arm_dynarmic_32: Log under Core_ARM instead of HW_GPU
2020-06-22 06:59:41 -04:00
ReinUsesLisp
778043a44c
arm_dynarmic_32: Fix implicit conversion error in SetTPIDR_EL0
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On MSVC builds we treat conversion warnings as errors.
2020-06-18 16:52:15 -03:00
MerryMage
109df7705f
arm_dynarmic_cp15: Update CP15
2020-06-17 17:10:24 +01:00
MerryMage
32a127faaa
arm_dynarmic_32: InterpreterFallback should never happen
2020-06-17 17:10:24 +01:00
bunnei
82d457af37
core: kernel: Move SVC to its own namesapce.
2020-04-17 00:59:28 -04:00
bunnei
c083ea7d78
core: Implement separate A32/A64 ARM interfaces.
2020-03-02 21:51:57 -05:00