45fb74d262
Makes the class interface consistent and provides accessors for obtaining a reference to the memory manager instance. Given we also return references, this makes our more flimsy uses of const apparent, given const doesn't propagate through pointers in the way one would typically expect. This makes our mutable state more apparent in some places.
151 lines
3.7 KiB
C++
151 lines
3.7 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <memory>
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#include <unordered_map>
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#include "common/common_types.h"
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#include "core/hle/service/nvflinger/buffer_queue.h"
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#include "video_core/memory_manager.h"
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra {
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enum class RenderTargetFormat : u32 {
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NONE = 0x0,
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RGBA32_FLOAT = 0xC0,
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RGBA32_UINT = 0xC2,
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RGBA16_UNORM = 0xC6,
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RGBA16_UINT = 0xC9,
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RGBA16_FLOAT = 0xCA,
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RG32_FLOAT = 0xCB,
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RG32_UINT = 0xCD,
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BGRA8_UNORM = 0xCF,
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RGB10_A2_UNORM = 0xD1,
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RGBA8_UNORM = 0xD5,
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RGBA8_SRGB = 0xD6,
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RGBA8_SNORM = 0xD7,
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RGBA8_UINT = 0xD9,
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RG16_UNORM = 0xDA,
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RG16_SNORM = 0xDB,
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RG16_SINT = 0xDC,
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RG16_UINT = 0xDD,
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RG16_FLOAT = 0xDE,
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R11G11B10_FLOAT = 0xE0,
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R32_UINT = 0xE4,
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R32_FLOAT = 0xE5,
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B5G6R5_UNORM = 0xE8,
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RG8_UNORM = 0xEA,
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RG8_SNORM = 0xEB,
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R16_UNORM = 0xEE,
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R16_SNORM = 0xEF,
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R16_SINT = 0xF0,
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R16_UINT = 0xF1,
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R16_FLOAT = 0xF2,
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R8_UNORM = 0xF3,
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R8_UINT = 0xF6,
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};
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enum class DepthFormat : u32 {
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Z32_FLOAT = 0xA,
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Z16_UNORM = 0x13,
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S8_Z24_UNORM = 0x14,
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Z24_X8_UNORM = 0x15,
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Z24_S8_UNORM = 0x16,
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Z24_C8_UNORM = 0x18,
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Z32_S8_X24_FLOAT = 0x19,
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};
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/// Returns the number of bytes per pixel of each rendertarget format.
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u32 RenderTargetBytesPerPixel(RenderTargetFormat format);
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/// Returns the number of bytes per pixel of each depth format.
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u32 DepthFormatBytesPerPixel(DepthFormat format);
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class DebugContext;
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/**
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* Struct describing framebuffer configuration
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*/
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struct FramebufferConfig {
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enum class PixelFormat : u32 {
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ABGR8 = 1,
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};
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/**
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* Returns the number of bytes per pixel.
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*/
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static u32 BytesPerPixel(PixelFormat format);
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VAddr address;
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u32 offset;
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u32 width;
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u32 height;
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u32 stride;
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PixelFormat pixel_format;
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using TransformFlags = Service::NVFlinger::BufferQueue::BufferTransformFlags;
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TransformFlags transform_flags;
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MathUtil::Rectangle<int> crop_rect;
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};
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namespace Engines {
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class Fermi2D;
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class Maxwell3D;
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class MaxwellCompute;
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class MaxwellDMA;
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} // namespace Engines
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enum class EngineID {
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FERMI_TWOD_A = 0x902D, // 2D Engine
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MAXWELL_B = 0xB197, // 3D Engine
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MAXWELL_COMPUTE_B = 0xB1C0,
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KEPLER_INLINE_TO_MEMORY_B = 0xA140,
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MAXWELL_DMA_COPY_A = 0xB0B5,
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};
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class GPU final {
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public:
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explicit GPU(VideoCore::RasterizerInterface& rasterizer);
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~GPU();
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/// Processes a command list stored at the specified address in GPU memory.
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void ProcessCommandList(GPUVAddr address, u32 size);
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/// Returns a reference to the Maxwell3D GPU engine.
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Engines::Maxwell3D& Maxwell3D();
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/// Returns a const reference to the Maxwell3D GPU engine.
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const Engines::Maxwell3D& Maxwell3D() const;
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/// Returns a reference to the GPU memory manager.
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Tegra::MemoryManager& MemoryManager();
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/// Returns a const reference to the GPU memory manager.
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const Tegra::MemoryManager& MemoryManager() const;
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private:
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/// Writes a single register in the engine bound to the specified subchannel
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void WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params);
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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/// Mapping of command subchannels to their bound engine ids.
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std::unordered_map<u32, EngineID> bound_engines;
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/// 3D engine
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std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
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/// 2D engine
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std::unique_ptr<Engines::Fermi2D> fermi_2d;
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/// Compute engine
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std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
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/// DMA engine
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std::unique_ptr<Engines::MaxwellDMA> maxwell_dma;
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};
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} // namespace Tegra
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