409 lines
19 KiB
C++
409 lines
19 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <boost/range/algorithm/fill.hpp>
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#include "common/profiler.h"
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#include "clipper.h"
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#include "command_processor.h"
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#include "math.h"
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#include "pica.h"
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#include "primitive_assembly.h"
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#include "vertex_shader.h"
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#include "video_core.h"
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#include "core/hle/service/gsp_gpu.h"
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#include "core/hw/gpu.h"
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#include "core/settings.h"
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#include "debug_utils/debug_utils.h"
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namespace Pica {
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namespace CommandProcessor {
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static int float_regs_counter = 0;
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static u32 uniform_write_buffer[4];
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static int default_attr_counter = 0;
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static u32 default_attr_write_buffer[3];
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Common::Profiling::TimingCategory category_drawing("Drawing");
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static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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auto& regs = g_state.regs;
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if (id >= regs.NumIds())
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return;
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// If we're skipping this frame, only allow trigger IRQ
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if (GPU::g_skip_frame && id != PICA_REG_INDEX(trigger_irq))
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return;
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// TODO: Figure out how register masking acts on e.g. vs_uniform_setup.set_value
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u32 old_value = regs[id];
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regs[id] = (old_value & ~mask) | (value & mask);
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::CommandLoaded, reinterpret_cast<void*>(&id));
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DebugUtils::OnPicaRegWrite(id, regs[id]);
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switch(id) {
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// Trigger IRQ
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case PICA_REG_INDEX(trigger_irq):
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::P3D);
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break;
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case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[0], 0x23c):
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case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[1], 0x23d):
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{
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unsigned index = id - PICA_REG_INDEX(command_buffer.trigger[0]);
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u32* head_ptr = (u32*)Memory::GetPhysicalPointer(regs.command_buffer.GetPhysicalAddress(index));
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = head_ptr;
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g_state.cmd_list.length = regs.command_buffer.GetSize(index) / sizeof(u32);
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break;
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}
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// It seems like these trigger vertex rendering
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case PICA_REG_INDEX(trigger_draw):
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case PICA_REG_INDEX(trigger_draw_indexed):
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{
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Common::Profiling::ScopeTimer scope_timer(category_drawing);
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DebugUtils::DumpTevStageConfig(regs.GetTevStages());
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::IncomingPrimitiveBatch, nullptr);
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const auto& attribute_config = regs.vertex_attributes;
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const u32 base_address = attribute_config.GetPhysicalBaseAddress();
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// Information about internal vertex attributes
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u32 vertex_attribute_sources[16];
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boost::fill(vertex_attribute_sources, 0xdeadbeef);
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u32 vertex_attribute_strides[16] = {};
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Regs::VertexAttributeFormat vertex_attribute_formats[16] = {};
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u32 vertex_attribute_elements[16] = {};
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u32 vertex_attribute_element_size[16] = {};
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// Setup attribute data from loaders
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for (int loader = 0; loader < 12; ++loader) {
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const auto& loader_config = attribute_config.attribute_loaders[loader];
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u32 load_address = base_address + loader_config.data_offset;
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// TODO: What happens if a loader overwrites a previous one's data?
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for (unsigned component = 0; component < loader_config.component_count; ++component) {
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u32 attribute_index = loader_config.GetComponent(component);
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vertex_attribute_sources[attribute_index] = load_address;
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vertex_attribute_strides[attribute_index] = static_cast<u32>(loader_config.byte_count);
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vertex_attribute_formats[attribute_index] = attribute_config.GetFormat(attribute_index);
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vertex_attribute_elements[attribute_index] = attribute_config.GetNumElements(attribute_index);
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vertex_attribute_element_size[attribute_index] = attribute_config.GetElementSizeInBytes(attribute_index);
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load_address += attribute_config.GetStride(attribute_index);
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}
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}
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// Load vertices
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bool is_indexed = (id == PICA_REG_INDEX(trigger_draw_indexed));
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const auto& index_info = regs.index_array;
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const u8* index_address_8 = Memory::GetPhysicalPointer(base_address + index_info.offset);
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const u16* index_address_16 = (u16*)index_address_8;
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bool index_u16 = index_info.format != 0;
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DebugUtils::GeometryDumper geometry_dumper;
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PrimitiveAssembler<VertexShader::OutputVertex> primitive_assembler(regs.triangle_topology.Value());
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PrimitiveAssembler<DebugUtils::GeometryDumper::Vertex> dumping_primitive_assembler(regs.triangle_topology.Value());
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for (unsigned int index = 0; index < regs.num_vertices; ++index)
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{
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unsigned int vertex = is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index]) : index;
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if (is_indexed) {
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// TODO: Implement some sort of vertex cache!
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}
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// Initialize data for the current vertex
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VertexShader::InputVertex input;
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// Load a debugging token to check whether this gets loaded by the running
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// application or not.
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static const float24 debug_token = float24::FromRawFloat24(0x00abcdef);
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input.attr[0].w = debug_token;
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for (int i = 0; i < attribute_config.GetNumTotalAttributes(); ++i) {
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// Load the default attribute if we're configured to do so, this data will be overwritten by the loader data if it's set
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if (attribute_config.IsDefaultAttribute(i)) {
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input.attr[i] = g_state.vs.default_attributes[i];
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LOG_TRACE(HW_GPU, "Loaded default attribute %x for vertex %x (index %x): (%f, %f, %f, %f)",
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i, vertex, index,
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input.attr[i][0].ToFloat32(), input.attr[i][1].ToFloat32(),
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input.attr[i][2].ToFloat32(), input.attr[i][3].ToFloat32());
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}
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// Load per-vertex data from the loader arrays
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for (unsigned int comp = 0; comp < vertex_attribute_elements[i]; ++comp) {
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const u8* srcdata = Memory::GetPhysicalPointer(vertex_attribute_sources[i] + vertex_attribute_strides[i] * vertex + comp * vertex_attribute_element_size[i]);
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const float srcval = (vertex_attribute_formats[i] == Regs::VertexAttributeFormat::BYTE) ? *(s8*)srcdata :
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(vertex_attribute_formats[i] == Regs::VertexAttributeFormat::UBYTE) ? *(u8*)srcdata :
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(vertex_attribute_formats[i] == Regs::VertexAttributeFormat::SHORT) ? *(s16*)srcdata :
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*(float*)srcdata;
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input.attr[i][comp] = float24::FromFloat32(srcval);
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LOG_TRACE(HW_GPU, "Loaded component %x of attribute %x for vertex %x (index %x) from 0x%08x + 0x%08lx + 0x%04lx: %f",
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comp, i, vertex, index,
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attribute_config.GetPhysicalBaseAddress(),
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vertex_attribute_sources[i] - base_address,
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vertex_attribute_strides[i] * vertex + comp * vertex_attribute_element_size[i],
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input.attr[i][comp].ToFloat32());
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}
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}
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// HACK: Some games do not initialize the vertex position's w component. This leads
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// to critical issues since it messes up perspective division. As a
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// workaround, we force the fourth component to 1.0 if we find this to be the
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// case.
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// To do this, we additionally have to assume that the first input attribute
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// is the vertex position, since there's no information about this other than
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// the empiric observation that this is usually the case.
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if (input.attr[0].w == debug_token)
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input.attr[0].w = float24::FromFloat32(1.0);
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexLoaded, (void*)&input);
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// NOTE: When dumping geometry, we simply assume that the first input attribute
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// corresponds to the position for now.
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DebugUtils::GeometryDumper::Vertex dumped_vertex = {
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input.attr[0][0].ToFloat32(), input.attr[0][1].ToFloat32(), input.attr[0][2].ToFloat32()
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};
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using namespace std::placeholders;
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dumping_primitive_assembler.SubmitVertex(dumped_vertex,
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std::bind(&DebugUtils::GeometryDumper::AddTriangle,
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&geometry_dumper, _1, _2, _3));
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// Send to vertex shader
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VertexShader::OutputVertex output = VertexShader::RunShader(input, attribute_config.GetNumTotalAttributes());
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if (is_indexed) {
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// TODO: Add processed vertex to vertex cache!
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}
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if (Settings::values.use_hw_renderer) {
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// Send to hardware renderer
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static auto AddHWTriangle = [](const Pica::VertexShader::OutputVertex& v0,
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const Pica::VertexShader::OutputVertex& v1,
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const Pica::VertexShader::OutputVertex& v2) {
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VideoCore::g_renderer->hw_rasterizer->AddTriangle(v0, v1, v2);
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};
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primitive_assembler.SubmitVertex(output, AddHWTriangle);
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} else {
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// Send to triangle clipper
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primitive_assembler.SubmitVertex(output, Clipper::ProcessTriangle);
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}
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}
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if (Settings::values.use_hw_renderer) {
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VideoCore::g_renderer->hw_rasterizer->DrawTriangles();
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}
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geometry_dumper.Dump();
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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break;
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}
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case PICA_REG_INDEX(vs_bool_uniforms):
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for (unsigned i = 0; i < 16; ++i)
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g_state.vs.uniforms.b[i] = (regs.vs_bool_uniforms.Value() & (1 << i)) != 0;
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break;
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[0], 0x2b1):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[1], 0x2b2):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[2], 0x2b3):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[3], 0x2b4):
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{
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int index = (id - PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[0], 0x2b1));
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auto values = regs.vs_int_uniforms[index];
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g_state.vs.uniforms.i[index] = Math::Vec4<u8>(values.x, values.y, values.z, values.w);
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LOG_TRACE(HW_GPU, "Set integer uniform %d to %02x %02x %02x %02x",
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index, values.x.Value(), values.y.Value(), values.z.Value(), values.w.Value());
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break;
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}
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[0], 0x2c1):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[1], 0x2c2):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[2], 0x2c3):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[3], 0x2c4):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[4], 0x2c5):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[5], 0x2c6):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[6], 0x2c7):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[7], 0x2c8):
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{
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auto& uniform_setup = regs.vs_uniform_setup;
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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uniform_write_buffer[float_regs_counter++] = value;
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// Uniforms are written in a packed format such that four float24 values are encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) ||
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(float_regs_counter >= 3 && !uniform_setup.IsFloat32())) {
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float_regs_counter = 0;
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auto& uniform = g_state.vs.uniforms.f[uniform_setup.index];
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if (uniform_setup.index > 95) {
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LOG_ERROR(HW_GPU, "Invalid VS uniform index %d", (int)uniform_setup.index);
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break;
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}
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// NOTE: The destination component order indeed is "backwards"
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if (uniform_setup.IsFloat32()) {
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for (auto i : {0,1,2,3})
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uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i]));
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} else {
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// TODO: Untested
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uniform.w = float24::FromRawFloat24(uniform_write_buffer[0] >> 8);
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uniform.z = float24::FromRawFloat24(((uniform_write_buffer[0] & 0xFF)<<16) | ((uniform_write_buffer[1] >> 16) & 0xFFFF));
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uniform.y = float24::FromRawFloat24(((uniform_write_buffer[1] & 0xFFFF)<<8) | ((uniform_write_buffer[2] >> 24) & 0xFF));
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uniform.x = float24::FromRawFloat24(uniform_write_buffer[2] & 0xFFFFFF);
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}
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LOG_TRACE(HW_GPU, "Set uniform %x to (%f %f %f %f)", (int)uniform_setup.index,
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uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(),
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uniform.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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uniform_setup.index = uniform_setup.index + 1;
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}
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break;
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}
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// Load default vertex input attributes
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case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[0], 0x233):
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case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[1], 0x234):
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case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[2], 0x235):
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{
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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default_attr_write_buffer[default_attr_counter++] = value;
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// Default attributes are written in a packed format such that four float24 values are encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if (default_attr_counter >= 3) {
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default_attr_counter = 0;
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auto& setup = regs.vs_default_attributes_setup;
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if (setup.index >= 16) {
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LOG_ERROR(HW_GPU, "Invalid VS default attribute index %d", (int)setup.index);
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break;
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}
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Math::Vec4<float24>& attribute = g_state.vs.default_attributes[setup.index];
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// NOTE: The destination component order indeed is "backwards"
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attribute.w = float24::FromRawFloat24(default_attr_write_buffer[0] >> 8);
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attribute.z = float24::FromRawFloat24(((default_attr_write_buffer[0] & 0xFF) << 16) | ((default_attr_write_buffer[1] >> 16) & 0xFFFF));
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attribute.y = float24::FromRawFloat24(((default_attr_write_buffer[1] & 0xFFFF) << 8) | ((default_attr_write_buffer[2] >> 24) & 0xFF));
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attribute.x = float24::FromRawFloat24(default_attr_write_buffer[2] & 0xFFFFFF);
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LOG_TRACE(HW_GPU, "Set default VS attribute %x to (%f %f %f %f)", (int)setup.index,
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attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
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attribute.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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setup.index = setup.index + 1;
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}
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break;
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}
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// Load shader program code
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[2], 0x2ce):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[3], 0x2cf):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[4], 0x2d0):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[5], 0x2d1):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[6], 0x2d2):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[7], 0x2d3):
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{
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g_state.vs.program_code[regs.vs_program.offset] = value;
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regs.vs_program.offset++;
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break;
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}
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// Load swizzle pattern data
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[0], 0x2d6):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[1], 0x2d7):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[2], 0x2d8):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[3], 0x2d9):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[4], 0x2da):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[5], 0x2db):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[6], 0x2dc):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[7], 0x2dd):
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{
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g_state.vs.swizzle_data[regs.vs_swizzle_patterns.offset] = value;
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regs.vs_swizzle_patterns.offset++;
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break;
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}
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default:
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break;
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}
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VideoCore::g_renderer->hw_rasterizer->NotifyPicaRegisterChanged(id);
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::CommandProcessed, reinterpret_cast<void*>(&id));
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}
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void ProcessCommandList(const u32* list, u32 size) {
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = list;
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g_state.cmd_list.length = size / sizeof(u32);
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while (g_state.cmd_list.current_ptr < g_state.cmd_list.head_ptr + g_state.cmd_list.length) {
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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static const u32 expand_bits_to_bytes[] = {
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0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
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0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
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0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
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0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
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};
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// Align read pointer to 8 bytes
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if ((g_state.cmd_list.head_ptr - g_state.cmd_list.current_ptr) % 2 != 0)
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++g_state.cmd_list.current_ptr;
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u32 value = *g_state.cmd_list.current_ptr++;
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const CommandHeader header = { *g_state.cmd_list.current_ptr++ };
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const u32 write_mask = expand_bits_to_bytes[header.parameter_mask];
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u32 cmd = header.cmd_id;
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WritePicaReg(cmd, value, write_mask);
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for (unsigned i = 0; i < header.extra_data_length; ++i) {
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u32 cmd = header.cmd_id + (header.group_commands ? i + 1 : 0);
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WritePicaReg(cmd, *g_state.cmd_list.current_ptr++, write_mask);
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}
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}
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}
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} // namespace
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} // namespace
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