fc6db97a09
Unicorn long-since lost most of its use, due to dynarmic gaining support for handling most instructions. At this point any further issues encountered should be used to make dynarmic better. This also allows us to remove our dependency on Python.
301 lines
10 KiB
C++
301 lines
10 KiB
C++
// Copyright 2020 yuzu emulator team
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cinttypes>
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#include <memory>
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#include <dynarmic/A32/a32.h>
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#include <dynarmic/A32/config.h>
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#include <dynarmic/A32/context.h>
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "common/page_table.h"
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#include "core/arm/cpu_interrupt_handler.h"
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#include "core/arm/dynarmic/arm_dynarmic_32.h"
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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#include "core/arm/dynarmic/arm_exclusive_monitor.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/svc.h"
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#include "core/memory.h"
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#include "core/settings.h"
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namespace Core {
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class DynarmicCallbacks32 : public Dynarmic::A32::UserCallbacks {
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public:
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explicit DynarmicCallbacks32(ARM_Dynarmic_32& parent) : parent(parent) {}
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u8 MemoryRead8(u32 vaddr) override {
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return parent.system.Memory().Read8(vaddr);
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}
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u16 MemoryRead16(u32 vaddr) override {
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return parent.system.Memory().Read16(vaddr);
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}
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u32 MemoryRead32(u32 vaddr) override {
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return parent.system.Memory().Read32(vaddr);
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}
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u64 MemoryRead64(u32 vaddr) override {
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return parent.system.Memory().Read64(vaddr);
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}
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void MemoryWrite8(u32 vaddr, u8 value) override {
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parent.system.Memory().Write8(vaddr, value);
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}
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void MemoryWrite16(u32 vaddr, u16 value) override {
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parent.system.Memory().Write16(vaddr, value);
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}
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void MemoryWrite32(u32 vaddr, u32 value) override {
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parent.system.Memory().Write32(vaddr, value);
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}
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void MemoryWrite64(u32 vaddr, u64 value) override {
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parent.system.Memory().Write64(vaddr, value);
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}
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bool MemoryWriteExclusive8(u32 vaddr, u8 value, u8 expected) override {
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return parent.system.Memory().WriteExclusive8(vaddr, value, expected);
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}
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bool MemoryWriteExclusive16(u32 vaddr, u16 value, u16 expected) override {
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return parent.system.Memory().WriteExclusive16(vaddr, value, expected);
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}
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bool MemoryWriteExclusive32(u32 vaddr, u32 value, u32 expected) override {
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return parent.system.Memory().WriteExclusive32(vaddr, value, expected);
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}
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bool MemoryWriteExclusive64(u32 vaddr, u64 value, u64 expected) override {
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return parent.system.Memory().WriteExclusive64(vaddr, value, expected);
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}
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void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
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UNIMPLEMENTED_MSG("This should never happen, pc = {:08X}, code = {:08X}", pc,
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MemoryReadCode(pc));
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}
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void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override {
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switch (exception) {
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case Dynarmic::A32::Exception::UndefinedInstruction:
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case Dynarmic::A32::Exception::UnpredictableInstruction:
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break;
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case Dynarmic::A32::Exception::Breakpoint:
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break;
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}
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LOG_CRITICAL(Core_ARM, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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static_cast<std::size_t>(exception), pc, MemoryReadCode(pc));
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UNIMPLEMENTED();
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}
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void CallSVC(u32 swi) override {
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Kernel::Svc::Call(parent.system, swi);
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}
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void AddTicks(u64 ticks) override {
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if (parent.uses_wall_clock) {
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return;
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}
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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// if not all cores are doing a similar amount of work. Instead of doing this, we should
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// device a way so that timing is consistent across all cores without increasing the ticks 4
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// times.
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u64 amortized_ticks =
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(ticks - num_interpreted_instructions) / Core::Hardware::NUM_CPU_CORES;
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// Always execute at least one tick.
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amortized_ticks = std::max<u64>(amortized_ticks, 1);
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parent.system.CoreTiming().AddTicks(amortized_ticks);
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num_interpreted_instructions = 0;
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}
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u64 GetTicksRemaining() override {
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if (parent.uses_wall_clock) {
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if (!parent.interrupt_handlers[parent.core_index].IsInterrupted()) {
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return minimum_run_cycles;
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}
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return 0U;
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}
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return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
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}
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ARM_Dynarmic_32& parent;
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std::size_t num_interpreted_instructions{};
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static constexpr u64 minimum_run_cycles = 1000U;
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};
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std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable& page_table,
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std::size_t address_space_bits) const {
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Dynarmic::A32::UserConfig config;
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config.callbacks = cb.get();
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// TODO(bunnei): Implement page table for 32-bit
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// config.page_table = &page_table.pointers;
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config.coprocessors[15] = cp15;
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config.define_unpredictable_behaviour = true;
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static constexpr std::size_t PAGE_BITS = 12;
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static constexpr std::size_t NUM_PAGE_TABLE_ENTRIES = 1 << (32 - PAGE_BITS);
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config.page_table = reinterpret_cast<std::array<std::uint8_t*, NUM_PAGE_TABLE_ENTRIES>*>(
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page_table.pointers.data());
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config.absolute_offset_page_table = true;
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config.detect_misaligned_access_via_page_table = 16 | 32 | 64 | 128;
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config.only_detect_misalignment_via_page_table_on_page_boundary = true;
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// Multi-process state
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config.processor_id = core_index;
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config.global_monitor = &exclusive_monitor.monitor;
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// Timing
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config.wall_clock_cntpct = uses_wall_clock;
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// Safe optimizations
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if (Settings::values.cpu_accuracy == Settings::CPUAccuracy::DebugMode) {
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if (!Settings::values.cpuopt_page_tables) {
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config.page_table = nullptr;
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}
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if (!Settings::values.cpuopt_block_linking) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::BlockLinking;
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}
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if (!Settings::values.cpuopt_return_stack_buffer) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::ReturnStackBuffer;
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}
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if (!Settings::values.cpuopt_fast_dispatcher) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::FastDispatch;
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}
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if (!Settings::values.cpuopt_context_elimination) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::GetSetElimination;
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}
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if (!Settings::values.cpuopt_const_prop) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::ConstProp;
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}
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if (!Settings::values.cpuopt_misc_ir) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::MiscIROpt;
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}
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if (!Settings::values.cpuopt_reduce_misalign_checks) {
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config.only_detect_misalignment_via_page_table_on_page_boundary = false;
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}
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}
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// Unsafe optimizations
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if (Settings::values.cpu_accuracy == Settings::CPUAccuracy::Unsafe) {
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config.unsafe_optimizations = true;
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if (Settings::values.cpuopt_unsafe_unfuse_fma) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_UnfuseFMA;
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}
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if (Settings::values.cpuopt_unsafe_reduce_fp_error) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_ReducedErrorFP;
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}
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}
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return std::make_unique<Dynarmic::A32::Jit>(config);
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}
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void ARM_Dynarmic_32::Run() {
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jit->Run();
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}
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void ARM_Dynarmic_32::Step() {
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jit->Step();
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}
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ARM_Dynarmic_32::ARM_Dynarmic_32(System& system, CPUInterrupts& interrupt_handlers,
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bool uses_wall_clock, ExclusiveMonitor& exclusive_monitor,
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std::size_t core_index)
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: ARM_Interface{system, interrupt_handlers, uses_wall_clock},
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cb(std::make_unique<DynarmicCallbacks32>(*this)),
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cp15(std::make_shared<DynarmicCP15>(*this)), core_index{core_index},
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exclusive_monitor{dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor)} {}
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ARM_Dynarmic_32::~ARM_Dynarmic_32() = default;
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void ARM_Dynarmic_32::SetPC(u64 pc) {
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jit->Regs()[15] = static_cast<u32>(pc);
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}
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u64 ARM_Dynarmic_32::GetPC() const {
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return jit->Regs()[15];
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}
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u64 ARM_Dynarmic_32::GetReg(int index) const {
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return jit->Regs()[index];
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}
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void ARM_Dynarmic_32::SetReg(int index, u64 value) {
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jit->Regs()[index] = static_cast<u32>(value);
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}
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u128 ARM_Dynarmic_32::GetVectorReg(int index) const {
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return {};
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}
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void ARM_Dynarmic_32::SetVectorReg(int index, u128 value) {}
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u32 ARM_Dynarmic_32::GetPSTATE() const {
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return jit->Cpsr();
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}
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void ARM_Dynarmic_32::SetPSTATE(u32 cpsr) {
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jit->SetCpsr(cpsr);
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}
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u64 ARM_Dynarmic_32::GetTlsAddress() const {
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return cp15->uro;
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}
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void ARM_Dynarmic_32::SetTlsAddress(VAddr address) {
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cp15->uro = static_cast<u32>(address);
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}
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u64 ARM_Dynarmic_32::GetTPIDR_EL0() const {
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return cp15->uprw;
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}
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void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
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cp15->uprw = static_cast<u32>(value);
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}
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void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) {
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jit->ChangeProcessorID(new_core_id);
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}
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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jit->SaveContext(context);
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ctx.cpu_registers = context.Regs();
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ctx.extension_registers = context.ExtRegs();
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ctx.cpsr = context.Cpsr();
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ctx.fpscr = context.Fpscr();
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}
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void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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context.Regs() = ctx.cpu_registers;
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context.ExtRegs() = ctx.extension_registers;
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context.SetCpsr(ctx.cpsr);
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context.SetFpscr(ctx.fpscr);
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jit->LoadContext(context);
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}
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void ARM_Dynarmic_32::PrepareReschedule() {
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jit->HaltExecution();
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}
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void ARM_Dynarmic_32::ClearInstructionCache() {
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if (!jit) {
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return;
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}
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jit->ClearCache();
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}
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void ARM_Dynarmic_32::ClearExclusiveState() {
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jit->ClearExclusiveState();
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}
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void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
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std::size_t new_address_space_size_in_bits) {
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auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
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auto iter = jit_cache.find(key);
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if (iter != jit_cache.end()) {
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jit = iter->second;
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return;
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}
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jit = MakeJit(page_table, new_address_space_size_in_bits);
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jit_cache.emplace(key, jit);
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}
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} // namespace Core
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