210 lines
5.5 KiB
C++
210 lines
5.5 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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Id Decorate(EmitContext& ctx, IR::Inst* inst, Id op) {
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const auto flags{inst->Flags<IR::FpControl>()};
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if (flags.no_contraction) {
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ctx.Decorate(op, spv::Decoration::NoContraction);
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}
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return op;
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}
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} // Anonymous namespace
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Id EmitFPAbs16(EmitContext& ctx, Id value) {
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return ctx.OpFAbs(ctx.F16[1], value);
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}
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Id EmitFPAbs32(EmitContext& ctx, Id value) {
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return ctx.OpFAbs(ctx.F32[1], value);
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}
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Id EmitFPAbs64(EmitContext& ctx, Id value) {
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return ctx.OpFAbs(ctx.F64[1], value);
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}
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Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFAdd(ctx.F16[1], a, b));
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}
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Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFAdd(ctx.F32[1], a, b));
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}
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Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFAdd(ctx.F64[1], a, b));
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}
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Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
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return Decorate(ctx, inst, ctx.OpFma(ctx.F16[1], a, b, c));
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}
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Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
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return Decorate(ctx, inst, ctx.OpFma(ctx.F32[1], a, b, c));
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}
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Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
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return Decorate(ctx, inst, ctx.OpFma(ctx.F64[1], a, b, c));
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}
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void EmitFPMax32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPMax64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPMin32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPMin64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFMul(ctx.F16[1], a, b));
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}
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Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFMul(ctx.F32[1], a, b));
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}
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Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return Decorate(ctx, inst, ctx.OpFMul(ctx.F64[1], a, b));
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}
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Id EmitFPNeg16(EmitContext& ctx, Id value) {
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return ctx.OpFNegate(ctx.F16[1], value);
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}
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Id EmitFPNeg32(EmitContext& ctx, Id value) {
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return ctx.OpFNegate(ctx.F32[1], value);
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}
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Id EmitFPNeg64(EmitContext& ctx, Id value) {
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return ctx.OpFNegate(ctx.F64[1], value);
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}
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void EmitFPRecip32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPRecip64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPRecipSqrt32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPRecipSqrt64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPSqrt(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPSin(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPSinNotReduced(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPExp2(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPExp2NotReduced(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPCos(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPCosNotReduced(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitFPLog2(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitFPSaturate16(EmitContext& ctx, Id value) {
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const Id zero{ctx.Constant(ctx.F16[1], u16{0})};
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const Id one{ctx.Constant(ctx.F16[1], u16{0x3c00})};
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return ctx.OpFClamp(ctx.F32[1], value, zero, one);
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}
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Id EmitFPSaturate32(EmitContext& ctx, Id value) {
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const Id zero{ctx.Constant(ctx.F32[1], f32{0.0})};
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const Id one{ctx.Constant(ctx.F32[1], f32{1.0})};
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return ctx.OpFClamp(ctx.F32[1], value, zero, one);
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}
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Id EmitFPSaturate64(EmitContext& ctx, Id value) {
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const Id zero{ctx.Constant(ctx.F64[1], f64{0.0})};
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const Id one{ctx.Constant(ctx.F64[1], f64{1.0})};
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return ctx.OpFClamp(ctx.F64[1], value, zero, one);
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}
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Id EmitFPRoundEven16(EmitContext& ctx, Id value) {
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return ctx.OpRoundEven(ctx.F16[1], value);
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}
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Id EmitFPRoundEven32(EmitContext& ctx, Id value) {
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return ctx.OpRoundEven(ctx.F32[1], value);
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}
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Id EmitFPRoundEven64(EmitContext& ctx, Id value) {
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return ctx.OpRoundEven(ctx.F64[1], value);
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}
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Id EmitFPFloor16(EmitContext& ctx, Id value) {
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return ctx.OpFloor(ctx.F16[1], value);
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}
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Id EmitFPFloor32(EmitContext& ctx, Id value) {
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return ctx.OpFloor(ctx.F32[1], value);
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}
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Id EmitFPFloor64(EmitContext& ctx, Id value) {
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return ctx.OpFloor(ctx.F64[1], value);
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}
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Id EmitFPCeil16(EmitContext& ctx, Id value) {
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return ctx.OpCeil(ctx.F16[1], value);
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}
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Id EmitFPCeil32(EmitContext& ctx, Id value) {
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return ctx.OpCeil(ctx.F32[1], value);
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}
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Id EmitFPCeil64(EmitContext& ctx, Id value) {
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return ctx.OpCeil(ctx.F64[1], value);
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}
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Id EmitFPTrunc16(EmitContext& ctx, Id value) {
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return ctx.OpTrunc(ctx.F16[1], value);
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}
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Id EmitFPTrunc32(EmitContext& ctx, Id value) {
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return ctx.OpTrunc(ctx.F32[1], value);
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}
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Id EmitFPTrunc64(EmitContext& ctx, Id value) {
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return ctx.OpTrunc(ctx.F64[1], value);
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}
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} // namespace Shader::Backend::SPIRV
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