99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
237 lines
9.6 KiB
C++
237 lines
9.6 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <utility>
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#include "shader_recompiler/ir_opt/passes.h"
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namespace Shader::Optimization {
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namespace {
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std::pair<IR::U32, IR::U32> Unpack(IR::IREmitter& ir, const IR::Value& packed) {
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if (packed.IsImmediate()) {
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const u64 value{packed.U64()};
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return {
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ir.Imm32(static_cast<u32>(value)),
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ir.Imm32(static_cast<u32>(value >> 32)),
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};
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} else {
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return std::pair<IR::U32, IR::U32>{
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ir.CompositeExtract(packed, 0u),
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ir.CompositeExtract(packed, 1u),
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};
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}
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}
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void IAdd64To32(IR::Block& block, IR::Inst& inst) {
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if (inst.HasAssociatedPseudoOperation()) {
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throw NotImplementedException("IAdd64 emulation with pseudo instructions");
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}
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IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
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const auto [a_lo, a_hi]{Unpack(ir, inst.Arg(0))};
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const auto [b_lo, b_hi]{Unpack(ir, inst.Arg(1))};
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const IR::U32 ret_lo{ir.IAdd(a_lo, b_lo)};
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const IR::U32 carry{ir.Select(ir.GetCarryFromOp(ret_lo), ir.Imm32(1u), ir.Imm32(0u))};
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const IR::U32 ret_hi{ir.IAdd(ir.IAdd(a_hi, b_hi), carry)};
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inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
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}
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void ISub64To32(IR::Block& block, IR::Inst& inst) {
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if (inst.HasAssociatedPseudoOperation()) {
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throw NotImplementedException("ISub64 emulation with pseudo instructions");
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}
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IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
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const auto [a_lo, a_hi]{Unpack(ir, inst.Arg(0))};
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const auto [b_lo, b_hi]{Unpack(ir, inst.Arg(1))};
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const IR::U32 ret_lo{ir.ISub(a_lo, b_lo)};
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const IR::U1 underflow{ir.IGreaterThan(ret_lo, a_lo, false)};
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const IR::U32 underflow_bit{ir.Select(underflow, ir.Imm32(1u), ir.Imm32(0u))};
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const IR::U32 ret_hi{ir.ISub(ir.ISub(a_hi, b_hi), underflow_bit)};
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inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
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}
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void INeg64To32(IR::Block& block, IR::Inst& inst) {
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if (inst.HasAssociatedPseudoOperation()) {
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throw NotImplementedException("INeg64 emulation with pseudo instructions");
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}
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IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
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auto [lo, hi]{Unpack(ir, inst.Arg(0))};
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lo = ir.BitwiseNot(lo);
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hi = ir.BitwiseNot(hi);
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lo = ir.IAdd(lo, ir.Imm32(1));
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const IR::U32 carry{ir.Select(ir.GetCarryFromOp(lo), ir.Imm32(1u), ir.Imm32(0u))};
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hi = ir.IAdd(hi, carry);
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inst.ReplaceUsesWith(ir.CompositeConstruct(lo, hi));
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}
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void ShiftLeftLogical64To32(IR::Block& block, IR::Inst& inst) {
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if (inst.HasAssociatedPseudoOperation()) {
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throw NotImplementedException("ShiftLeftLogical64 emulation with pseudo instructions");
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}
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IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
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const auto [lo, hi]{Unpack(ir, inst.Arg(0))};
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const IR::U32 shift{inst.Arg(1)};
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const IR::U32 shifted_lo{ir.ShiftLeftLogical(lo, shift)};
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const IR::U32 shifted_hi{ir.ShiftLeftLogical(hi, shift)};
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const IR::U32 inv_shift{ir.ISub(shift, ir.Imm32(32))};
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const IR::U1 is_long{ir.IGreaterThanEqual(inv_shift, ir.Imm32(0), true)};
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const IR::U1 is_zero{ir.IEqual(shift, ir.Imm32(0))};
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const IR::U32 long_ret_lo{ir.Imm32(0)};
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const IR::U32 long_ret_hi{ir.ShiftLeftLogical(lo, inv_shift)};
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const IR::U32 shift_complement{ir.ISub(ir.Imm32(32), shift)};
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const IR::U32 lo_extract{ir.BitFieldExtract(lo, shift_complement, shift, false)};
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const IR::U32 short_ret_lo{shifted_lo};
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const IR::U32 short_ret_hi{ir.BitwiseOr(shifted_hi, lo_extract)};
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const IR::U32 zero_ret_lo{lo};
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const IR::U32 zero_ret_hi{hi};
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const IR::U32 non_zero_lo{ir.Select(is_long, long_ret_lo, short_ret_lo)};
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const IR::U32 non_zero_hi{ir.Select(is_long, long_ret_hi, short_ret_hi)};
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const IR::U32 ret_lo{ir.Select(is_zero, zero_ret_lo, non_zero_lo)};
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const IR::U32 ret_hi{ir.Select(is_zero, zero_ret_hi, non_zero_hi)};
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inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
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}
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void ShiftRightLogical64To32(IR::Block& block, IR::Inst& inst) {
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if (inst.HasAssociatedPseudoOperation()) {
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throw NotImplementedException("ShiftRightLogical64 emulation with pseudo instructions");
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}
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IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
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const auto [lo, hi]{Unpack(ir, inst.Arg(0))};
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const IR::U32 shift{inst.Arg(1)};
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const IR::U32 shifted_lo{ir.ShiftRightLogical(lo, shift)};
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const IR::U32 shifted_hi{ir.ShiftRightLogical(hi, shift)};
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const IR::U32 inv_shift{ir.ISub(shift, ir.Imm32(32))};
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const IR::U1 is_long{ir.IGreaterThanEqual(inv_shift, ir.Imm32(0), true)};
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const IR::U1 is_zero{ir.IEqual(shift, ir.Imm32(0))};
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const IR::U32 long_ret_hi{ir.Imm32(0)};
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const IR::U32 long_ret_lo{ir.ShiftRightLogical(hi, inv_shift)};
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const IR::U32 shift_complement{ir.ISub(ir.Imm32(32), shift)};
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const IR::U32 short_hi_extract{ir.BitFieldExtract(hi, ir.Imm32(0), shift)};
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const IR::U32 short_ret_hi{shifted_hi};
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const IR::U32 short_ret_lo{
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ir.BitFieldInsert(shifted_lo, short_hi_extract, shift_complement, shift)};
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const IR::U32 zero_ret_lo{lo};
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const IR::U32 zero_ret_hi{hi};
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const IR::U32 non_zero_lo{ir.Select(is_long, long_ret_lo, short_ret_lo)};
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const IR::U32 non_zero_hi{ir.Select(is_long, long_ret_hi, short_ret_hi)};
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const IR::U32 ret_lo{ir.Select(is_zero, zero_ret_lo, non_zero_lo)};
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const IR::U32 ret_hi{ir.Select(is_zero, zero_ret_hi, non_zero_hi)};
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inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
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}
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void ShiftRightArithmetic64To32(IR::Block& block, IR::Inst& inst) {
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if (inst.HasAssociatedPseudoOperation()) {
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throw NotImplementedException("ShiftRightArithmetic64 emulation with pseudo instructions");
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}
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IR::IREmitter ir(block, IR::Block::InstructionList::s_iterator_to(inst));
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const auto [lo, hi]{Unpack(ir, inst.Arg(0))};
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const IR::U32 shift{inst.Arg(1)};
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const IR::U32 shifted_lo{ir.ShiftRightLogical(lo, shift)};
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const IR::U32 shifted_hi{ir.ShiftRightArithmetic(hi, shift)};
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const IR::U32 sign_extension{ir.ShiftRightArithmetic(hi, ir.Imm32(31))};
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const IR::U32 inv_shift{ir.ISub(shift, ir.Imm32(32))};
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const IR::U1 is_long{ir.IGreaterThanEqual(inv_shift, ir.Imm32(0), true)};
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const IR::U1 is_zero{ir.IEqual(shift, ir.Imm32(0))};
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const IR::U32 long_ret_hi{sign_extension};
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const IR::U32 long_ret_lo{ir.ShiftRightArithmetic(hi, inv_shift)};
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const IR::U32 shift_complement{ir.ISub(ir.Imm32(32), shift)};
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const IR::U32 short_hi_extract(ir.BitFieldExtract(hi, ir.Imm32(0), shift));
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const IR::U32 short_ret_hi{shifted_hi};
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const IR::U32 short_ret_lo{
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ir.BitFieldInsert(shifted_lo, short_hi_extract, shift_complement, shift)};
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const IR::U32 zero_ret_lo{lo};
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const IR::U32 zero_ret_hi{hi};
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const IR::U32 non_zero_lo{ir.Select(is_long, long_ret_lo, short_ret_lo)};
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const IR::U32 non_zero_hi{ir.Select(is_long, long_ret_hi, short_ret_hi)};
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const IR::U32 ret_lo{ir.Select(is_zero, zero_ret_lo, non_zero_lo)};
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const IR::U32 ret_hi{ir.Select(is_zero, zero_ret_hi, non_zero_hi)};
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inst.ReplaceUsesWith(ir.CompositeConstruct(ret_lo, ret_hi));
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}
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void Lower(IR::Block& block, IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::PackUint2x32:
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case IR::Opcode::UnpackUint2x32:
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return inst.ReplaceOpcode(IR::Opcode::Identity);
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case IR::Opcode::IAdd64:
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return IAdd64To32(block, inst);
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case IR::Opcode::ISub64:
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return ISub64To32(block, inst);
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case IR::Opcode::INeg64:
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return INeg64To32(block, inst);
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case IR::Opcode::ShiftLeftLogical64:
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return ShiftLeftLogical64To32(block, inst);
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case IR::Opcode::ShiftRightLogical64:
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return ShiftRightLogical64To32(block, inst);
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case IR::Opcode::ShiftRightArithmetic64:
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return ShiftRightArithmetic64To32(block, inst);
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case IR::Opcode::SharedAtomicExchange64:
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return inst.ReplaceOpcode(IR::Opcode::SharedAtomicExchange32x2);
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case IR::Opcode::GlobalAtomicIAdd64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicIAdd32x2);
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case IR::Opcode::GlobalAtomicSMin64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicSMin32x2);
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case IR::Opcode::GlobalAtomicUMin64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicUMin32x2);
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case IR::Opcode::GlobalAtomicSMax64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicSMax32x2);
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case IR::Opcode::GlobalAtomicUMax64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicUMax32x2);
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case IR::Opcode::GlobalAtomicAnd64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicAnd32x2);
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case IR::Opcode::GlobalAtomicOr64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicOr32x2);
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case IR::Opcode::GlobalAtomicXor64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicXor32x2);
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case IR::Opcode::GlobalAtomicExchange64:
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return inst.ReplaceOpcode(IR::Opcode::GlobalAtomicExchange32x2);
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default:
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break;
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}
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}
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} // Anonymous namespace
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void LowerInt64ToInt32(IR::Program& program) {
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const auto end{program.post_order_blocks.rend()};
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for (auto it = program.post_order_blocks.rbegin(); it != end; ++it) {
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IR::Block* const block{*it};
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for (IR::Inst& inst : block->Instructions()) {
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Lower(*block, inst);
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}
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}
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}
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} // namespace Shader::Optimization
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